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參數(shù)資料
| 型號： | UPC1933GR |
| 廠商： | NEC Corp. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | DC-DC CONVERTER CONTROL IC |
| 中文描述： | 的DC - DC轉(zhuǎn)換器控制IC |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 119K |
| 代理商： | UPC1933GR |
Data Sheet G13690EJ3V0DS00
12
μ
PC1933
2.5
PWM Comparator
The output ON duty is controlled according to the outputs of the error amplifier.
A triangular waveform is input to the inverted pin, and the error amplifier output and Dead Time Control pin voltage (fixed
internally) are input to the non-inverted pins of the PWM comparator. Therefore, the output transistor ON period is the
period when the triangular waveform is lower than the error amplifier output and Dead Time Control pin voltage (fixed
internally) (refer to
Timing Chart
).
2.6
Timer Latch-Method Short Circuit Protection Circuit
When the output of the converter drops, the non-inverted input pin (1 pin) voltage of the error amplifier drops, and the
FB output of the error amplifier of the output goes high. If the FB output exceeds the timer latch input detection voltage
(V
TH
= 1.92 V), then the output of the SCP comparator goes low, and Q
1
goes off.
When Q
1
turns OFF, the constant-current supply charges C
DLY
via the DLY pin. The DLY pin is internally connected to a
flip-flop. When the DLY pin voltage reaches the UV detection voltage (V
UV
= 0.7 V (TYP)), the output Q of the flip-flop goes
low, and the output stage is latched to OFF (refer to
Figure 2-1 Block Diagram
).
Make the power supply voltage briefly less than the reset voltage (V
CCR
, 1.0 V TYP) to reset the latch circuit when the
short-circuit protection circuit has operated.
2.7
Output Circuit
The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum
rating), and an output current of 21 mA (absolute maximum rating).
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