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參數(shù)資料
| 型號： | UPC1851BCU |
| 廠商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C總線兼容美國的多邊貿(mào)易體制處理LSI |
| 文件頁數(shù)： | 22/60頁 |
| 文件大?。?/td> | 447K |
| 代理商： | UPC1851BCU |
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22
μ
PC1851B
Data Sheet S13417EJ2V0DS00
3. I
2
C BUS INTERFACE
The
μ
PC1851B uses a 2-wire serial bus developed by Philips. The serial clock line (SCL) and serial data line
(SDA) employ the 2-wire configuration as shown in Figure 3-1.
The
μ
PC1851B contains an I
2
C bus interface circuit, eleven (8-bit) read/write registers, and one read-only register.
Serial Clock Line (SCL)
The master CPU outputs a serial clock to achieve data synchronicity. The
μ
PC1851B receives serial data based
on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.
Serial Data Line (SDA)
The master CPU outputs data synchronously with the serial clock. The
μ
PC1851B receives this data based on
the serial clock. The input level is CMOS-compatible
Figure 3-1. Internal Equivalent Circuit of Interface Pins
For SCL and SDA pins, a protection diode on the V
CC
side is deleted not so as to pull the voltage of I
2
C bus line
down to 0 V while the power supply is off (V
CC
= 0 V).
SCL
SDA
R
P
R
P
PC1851B
μ
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