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1999
COMPOUND FIELD EFFECT POWER TRANSISTOR
μ
PA1560
N-CHANNEL POWER MOS FET ARRAY
SWITCHING
INDUSTRIAL USE
DATA SHEET
Document No.
Date Published
Printed in Japan
G14283EJ1V0DS00 (1st edition)
April 1999 NS CP(K)
DESCRIPTION
The
μ
PA1560 is N-Channel Power MOS FET Array
that built in 4 circuits designed for solenoid, motor and
lamp driver.
FEATURES
Full mold package with 4 circuits
4 V driving is possible
Low on-state resistance
R
DS(on)1
= 165 m
MAX. (V
GS
= 10 V, I
D
= 1.5 A)
R
DS(on)2
= 200 m
MAX. (V
GS
= 4 V, I
D
= 1.5 A)
Low input capacitance
C
iss
= 600 pF TYP.
ORDERING INFORMATION
PART NUMBER
PACKAGE
μ
PA1560H
10-pin SIP
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage (V
GS
= 0 V)
V
DSS
120
V
Gate to Source Voltage (V
DS
= 0 V)
V
GSS(AC)
±20
V
Gate to Source Voltage (V
DS
= 0 V)
V
GSS(DC)
+ 20, –10
V
Drain Current (DC)
Drain Current (pulse)
Note1
I
D(DC)
±3.0
A
I
D(pulse)
±12
A
Total Power Dissipation (T
C
= 25°C)
P
T1
28
W
Total Power Dissipation (T
A
= 25°C)
P
T2
3.7
W
Channel Temperature
T
ch
150
°C
Storage Temperature
Single Avalanche Current
Note2
Single Avalanche Energy
Note2
T
stg
–55 to + 150
°C
I
AS
3.0
A
E
AS
0.9
mJ
Notes 1.
PW
≤
10
μ
s, Duty Cycle
≤
1 %
2.
Starting T
ch
= 25
°C, V
DD
= 60
V, R
G
= 25
, V
GS
= 20
V
0
V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
PACKAGE DRAWING (Unit : mm)
26.8 MAX.
4.0
1
2
1.4
1 2 3 4 5 6 7 8 910
0.6±0.1
2.54
1.4
0.5±0.1
1
EQUIVALENT CIRCUIT
3
2
4
6
8
1
10
5
7
9
ELECTRODE CONNECTION
2, 4, 6, 8
3, 5, 7, 9
1, 10
: Source
: Gate
: Drain