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參數(shù)資料
| 型號(hào)： | UMA1022M |
| 廠(chǎng)商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Low cost dual frequency synthesizer for radio telephones |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2100 MHz, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT-266-1, SSOP-20 |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | UMA1022M |
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1998 Dec 09
6
Philips Semiconductors
Product specification
Low cost dual frequency synthesizer for
radio telephones
UMA1022M
Data format
The leading bits (dt15 to dt0) make up the data field, while
the trailing three bits (ad2 to ad0) comprise an address
field. The UMA1022M uses 4 of the 8 available addresses.
The data format is shown in Table 1. The first bit entered
is dt15, the last bit is ad0. For the divider ratios, the first
bits entered (P0 and R0) are the Least Significant Bits
(LSB).
This is different from previous Philips
synthesizers.
The trailing address bits are decoded on the rising edge of
E. This produces an internal load pulse to store the data in
the addressed latch. To avoid erroneous divider ratios, the
load pulse is not allowed during data reads by the
frequency dividers. This condition is guaranteed by
respecting a minimum E pulse width after data
transfer.The test register bits should not normally be
programmed active (HIGH); normal operation requires
them set LOW. When the supply voltage is established an
internal power-up initialization pulse is generated to
preconfigure the circuit state. Production testing does not
verify that all bits are preconfigured correctly.
Power-down mode
The RF and IF synthesizers are
on
when respectively the
input signal ON
A
and ON
B
are HIGH. When turned
on
, the
dividers and phase detector are synchronized to avoid
random phase errors. When turned
off
, the phase detector
is synchronized to avoid interrupting charge pump pulses.
The UMA1022M has a very low current consumption in the
power-down mode.
Table 1
Bit allocation; note 1
Notes
1.
2.
3.
4.
X = don’t care.
The test bits (at address 011) should not be programmed with any other value except all zeros for normal operation.
Bit XON = power-on of crystal oscillator low-noise amplifier; logic 1 turns
on
circuit block.
Bit P/A = 1 selects the output of the reference subdivider to the RF synthesizer and the output of the common
reference divider to the IF synthesizer.
The coefficient REFDIV2 (4 bits) selects the phase comparison ratio (1 to 16) between IF and RF synthesizers
(see Table 2).
P0 is the LSB of the RF main divider coefficient; R0 is the LSB of the reference divider coefficient; A0 is the LSB of
the IF main divider.
5.
6.
FIRST IN
REGISTER BIT ALLOCATION
LAST IN
DATA FIELD
ADDRESS
dt15
dt14
Test bits
(2)
dt13
dt12
dt11
dt10
dt9
dt8 dt7 dt6 dt5
dt4
P/A
(4)
dt3 dt2 dt1
REFDIV2
(5)
dt0
ad2
ad1
ad0
CPI
S/D
XON
(3)
X
X
X
X
0
0
0
0
1
0
0
1
1
0
1
0
P0
(6)
X
X
RF synthesizer main divider coefficient
X
X
R0
(6)
IF synthesizer main divider coefficient
P15
R9
A13
X
X
X
X
reference divider coefficient
A0
(6)
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