October 1992
7
Philips Semiconductors
Product specification
Low-power frequency synthesizer for
mobile radio communications
UMA1014
MAIN CONTROL
The control part consists mainly of the I
2
C-bus control
interface and a set of four registers A, B, C and D. The
serial input data (SDA) is converted into 8-bit parallel
words and stored in the appropriate registers. The data
transmission to the synthesizer is executed in the burst
mode with the following format:
//slave addr./subaddr./data1/data2/.../datan//; n up to 4
Data byte 1 is written in the register indicated by the
subaddress. An auto-increment circuit, if enabled
(AVI = 1), then provides the correct addressing for the
ensuing data bytes. Since the length of the data burst is
not fixed, it is possible to program only one register or the
whole set. The registers are structured in such a way so
that the burst, for normal operation, is kept as short as
possible. The bits that are only programmed during the
set-up (reference division ratio, power-down, phase
inversion and current on PCD) are stored in registers A
and B.
In the slave address six bits are fixed, the remaining two
bits depend on the application.
Table 4
Slave address
1
1
0
0
0
1
SAA
R/W
SAA is the slave address. When SAA goes HIGH then
SAA = 0, when SAA goes LOW then SAA = 1. This allows
the use of two UMA1014s on the same bus but using a
different address. R/W should be set to logic 0 when
writing to the synthesizer or set to logic 1 when reading the
status register.
The subaddress includes the register pointer, and sets the
two flags related to the auto-increment (AVI) and the alarm
disable (DI).
Table 5
Subaddress
X
X
X
DI
AVI
X
SB1
SB0
Where
:
X = not used
DI (Disable Interrupt):
DI = 1 disables the alarm on SYA
DI = 0 enables the alarm.
AVI (Auto Value Increment):
AVI = 1 enables the automatic increment
AVI = 0 disables the auto-increment.
SB1/SB0 are the pointers of the register where DATA1 will
be written (see Table 6).
When the auto-increment is disabled (AVI = 0), the
subaddress pointer will maintain the same value during the
I
2
C-bus transfer. All the data bytes will then be written
consecutively in the register pointed by the subaddress.
Table 6
Pointer of the registers
SB1
SB0
REGISTER POINTED
0
0
1
1
0
1
0
1
A
B
C
D