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參數資料
| 型號： | UMA1005T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Dual low-power frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PDSO20 |
| 文件頁數： | 7/24頁 |
| 文件大?。?/td> | 88K |
| 代理商： | UMA1005T |
November 1994
7
Philips Semiconductors
Preliminary specification
Dual low-power frequency synthesizer
UMA1005T
Table 1
Description of symbols used in Fig.4
Notes
1.
2.
X = don’t care.
Not including reset cycles and fractional-N effects.
SYMBOL
BITS
(1)
FUNCTION
NM1
12
number of main divider cycles when prescaler is programmed in ratio
R1 (FB1 = 1; FB2 = 0); note 2
number of main divider cycles when prescaler is programmed in ratio
R2 (FB1 = 0; FB2 = 0); note 2
NM2
8 if PR = 01
4 if PR
≠
01
4 if PR = 1X
NM3
number of main divider cycles when prescaler is programmed in ratio
R3 (FB1 = 0; FB2 = 1); note 2
number of main divider cycles when prescaler is programmed in ratio
R4 (FB1 = 1; FB2 = 1); note 2
prescaler type in use:
PR = 01; modulus 2 prescaler
PR = 10; modulus 3 prescaler
PR = 11; modulus 4 prescaler
PR = 00; modulus 4 prescaler (inhibit ratio 3)
fractional-N increment
fraction-N modulus selection flag:
1 = modulo 8
0 = modulo 5
A word format selection flag:
0 = 24-bit A0 format
1 = 32-bit A1 format
binary current setting factor for main charge pumps
binary acceleration factor for proportional charge pump current
binary acceleration factor for integral charge pump current
main divider enable flag
auxiliary divider enable flag
reference select for main phase detector
reference select for auxiliary phase detector
reference divider ratio
auxiliary divider ratio
auxiliary prescaler mode:
PA = 0; divide-by-4
PA = 1; divide-by-1
NM4
4 if PR = 11 or 00
PR
2
NF
FMOD
3
1
LONG
1
CN
CL
CK
EM
EA
SM
SA
NR
NA
PA
8
2
4
1
1
2
2
9
9
1
Auxiliary variable divider
The input signal on INA is amplified to a logic level by a
single ended input buffer, which accepts LOW level AC
coupled input signals. This input stage is enabled if the
serial control bit EA = 1. Disabling means that all currents
in the input stage are switched off. A fixed divide by 4 is
enabled if PA = 0. This divider has been optimized to
accept a high-frequency (90 MHz at a supply voltage
range of 4.75 to 5.5 V) input signal. If PA = 1 this divider is
disabled and the input signal is fed directly to the second
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