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參數(shù)資料
| 型號： | UL62H256BSA55 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 55 ns, PDSO28 |
| 封裝： | 0.300 INCH, SOP-28 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 87K |
| 代理商： | UL62H256BSA55 |
5
November 26, 2002
UL62H256B
Switching Characteristics
Read Cycle
Symbol
35
55
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Read Cycle Time
tRC
tcR
35
55
ns
Address Access Time to Data Valid
tAA
ta(A)
35
55
ns
Chip Enable Access Time to Data Valid
tACE
ta(E)
35
55
ns
G LOW to Data Valid
tOE
ta(G)
15
25
ns
E HIGH to Output in High-Z
tHZCE
tdis(E)
12
15
ns
G HIGH to Output in High-Z
tHZOE
tdis(G)
12
15
ns
E LOW to Output in Low-Z
tLZCE
ten(E)
33
ns
G LOW to Output in Low-Z
tLZOE
ten(G)
00
ns
Output Hold Time from Address Change
tOH
tv(A)
33
ns
E LOW to Power-Up Time
tPU
00
ns
E HIGH to Power-Down Time
tPD
35
55
ns
Switching Characteristics
Write Cycle
Symbol
35
55
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Write Cycle Time
tWC
tcW
35
55
ns
Write Pulse Width
tWP
tw(W)
20
35
ns
Write Setup Time
tWP
tsu(W)
20
35
ns
Address Setup Time
tAS
tsu(A)
00
ns
Address Valid to End of Write
tAW
tsu(A-WH)
25
40
ns
Chip Enable Setup Time
tCW
tsu(E)
25
40
ns
Pulse Width Chip Enable to End of Write
tCW
tw(E)
25
40
ns
Data Setup Time
tDS
tsu(D)
15
25
ns
Data Hold Time
tDH
th(D)
00
ns
Address Hold from End of Write
tAH
th(A)
00
ns
W LOW to Output in High-Z
tHZWE
tdis(W)
15
20
ns
G HIGH to Output in High-Z
tHZOE
tdis(G)
12
15
ns
W HIGH to Output in Low-Z
tLZWE
ten(W)
00
ns
G LOW to Output in Low-Z
tLZOE
ten(G)
00
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UL631H256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256S2C35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256S2C35G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256S2C45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
| UL631H256S2C45G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Voltage SoftStore 32K x 8 nvSRAM |
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