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參數(shù)資料
| 型號： | UL62H256BS1K35 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 35 ns, PDSO28 |
| 封裝： | 0.330 INCH, SOP-28 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 82K |
| 代理商： | UL62H256BS1K35 |
4
September 26, 2002
UL62H256B
Switching Characteristics
Read Cycle
Symbol
35
55
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Read Cycle Time
t
RC
t
cR
35
55
ns
Address Access Time to Data Valid
t
AA
t
a(A)
35
55
ns
Chip Enable Access Time to Data Valid
t
ACE
t
a(E)
35
55
ns
G LOW to Data Valid
t
OE
t
a(G)
15
25
ns
E HIGH to Output in High-Z
t
HZCE
t
dis(E)
12
15
ns
G HIGH to Output in High-Z
t
HZOE
t
dis(G)
12
15
ns
E LOW to Output in Low-Z
t
LZCE
t
en(E)
3
3
ns
G LOW to Output in Low-Z
t
LZOE
t
en(G)
0
0
ns
Output Hold Time from Address Change
t
OH
t
v(A)
3
3
ns
E LOW to Power-Up Time
t
PU
0
0
ns
E HIGH to Power-Down Time
t
PD
35
55
ns
Switching Characteristics
Write Cycle
Symbol
35
55
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Write Cycle Time
t
WC
t
cW
35
55
ns
Write Pulse Width
t
WP
t
w(W)
20
35
ns
Write Setup Time
t
WP
t
su(W)
20
35
ns
Address Setup Time
t
AS
t
su(A)
0
0
ns
Address Valid to End of Write
t
AW
t
su(A-WH)
25
40
ns
Chip Enable Setup Time
t
CW
t
su(E)
25
40
ns
Pulse Width Chip Enable to End of Write
t
CW
t
w(E)
25
40
ns
Data Setup Time
t
DS
t
su(D)
15
25
ns
Data Hold Time
t
DH
t
h(D)
0
0
ns
Address Hold from End of Write
t
AH
t
h(A)
0
0
ns
W LOW to Output in High-Z
t
HZWE
t
dis(W)
15
20
ns
G HIGH to Output in High-Z
t
HZOE
t
dis(G)
12
15
ns
W HIGH to Output in Low-Z
t
LZWE
t
en(W)
0
0
ns
G LOW to Output in Low-Z
t
LZOE
t
en(G)
0
0
ns
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