參數(shù)資料
型號: UDA1380TT
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO32
封裝: 6.10 MM, 0.65 MM PITCH, PLASTIC, MO-153, SOT-487-1, TSSOP-32
文件頁數(shù): 41/68頁
文件大?。?/td> 426K
代理商: UDA1380TT
2004 Apr 22
46
NXP Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
Table 59 Microphone input VGA gain setting bits
7to4
default value 0000
3SEL_LNA
Line input select. A 1-bit value to set the multiplexer in the analog front-end to select
between the LNA or the enable-in input for the left ADC. When this bit is logic 0: select
line input. When this bit is logic 1: select LNA for the left ADC. Default value 0.
2SEL_MIC
Microphone input select. A 1-bit value to set the multiplexer at the ADC right
channel output (on bit-stream level) which selects either the right channel data or the
left channel data. In case only the microphone input is used, the microphone signal
can be applied to the decimator for both left and right. When this bit is logic 0: select
right channel ADC. When this bit is logic 1: select left channel ADC (for instance for
microphone input). Default value 0.
1SKIP_DCFIL
DC filter bypass. A 1-bit value set to skip the DC filter which is just before the
decimator. This DC filter is there to compensate for the DC offset added in the ADC (to
remove idle tones from the audio band). This DC signal added (the DC dither) must
not be amplified in order to prevent clipping. Therefore this DC offset is removed first.
When this bit is logic 0: DC filter enabled. When this bit is logic 1: DC filter bypassed.
Default value 1.
0
EN_DCFIL
DC filter enable. A 1-bit value set to enable the DC filter which is at the output of the
decimator (running at 1fs). When this bit is logic 0: DC filter disabled. When this bit is
logic 1: DC filter enabled. Default value 0.
VGA_CTRL3
VGA_CTRL2
VGA_CTRL1
VGA_CTRL0
LNA GAIN (dB)
0000
0 (default)
00012
00104
00116
01008
0101
10
0110
12
0111
14
1000
16
1001
18
1010
20
1011
22
1100
24
1101
26
1110
28
1111
30
BIT
SYMBOL
DESCRIPTION
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