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參數(shù)資料
| 型號： | UC3727QP |
| 英文描述： | DMOS full bridge driver |
| 中文描述： | 單外設(shè)驅(qū)動 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 414K |
| 代理商： | UC3727QP |
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output Driver (cont.)
Turn on Clamp Voltage
Fault Clamp Voltage
UVLO Saturation to V
EE
Rise and Fall Times
Turn On Sequence Timer
Clamped Driver Time
Blanking Time
Fault Manager
Clamped Driver Time
Fault Lock Off Time
FRPLY Saturation
FRPLY Leakage
Desaturation Detection Comparator
Input Offset Voltage (|vio|)
Input Bias Current
Delay to Output
Undervoltage Lock Out
V
CC
Threshold
V
CC
Hysteresis
V
EE
Threshold
V
EE
Hysteresis
Thermal Shutdown
Threshold
Hysteresis
Total Standby Current
I(V
CC
)
I(OUT) = -100mA
|I(OUT)| = 100mA
I(OUT) = 20mA,V
CC
no connection
Cl = 1n, CLAMP = V
CC
, R
OUT
= 3
(Note 1)
7
8
9
10
2
75
11
12.5
3
150
V
V
V
ns
(Note 1)
(Note 1)
0.4
3
1
5
1.7
7
μ
s
μ
s
(Note 1)
(Note 1)
I(FRPLY) = 10mA
FRPLY = V
CC
0.4
15
1
1.7
35
3
10
μ
s
μ
s
V
μ
A
25
1.8
0
V
CM
= V
EE
+2, V
CM
= V
CC
-2
0
20
10
mV
μ
A
ns
1.5
150
C(FRC) = 0 (Note 1)
14
15.5
0.35
5.5
1
17
V
V
V
V
4.
5
0.5
6.5
1.5
Not tested
Not tested
175
45
°
C
°
C
24
30
mA
Unless otherwise stated, these specifications apply for T
A
=
55
°
C to 125
°
C for the
UC1727, T
A
=
40
°
C to 85
°
C for the UC2727, T
A
= 0
°
C to 70
°
C for the UC3727,
R(TRC) = 54.9k, C(TRC) = 180pF, R(FRC) = 309K, C(FRC) = 200pF, V
CC
- V
EE
=
25V, CLAMP = 9V, T
A
= T
J,
and all voltages are measured with respect to COM.
ELECTRICAL CHARACTERISTICS:
APPLICATION INFORMATION
Figure 1 shows the rectification and detection scheme
used in the UC1727 to derive both power and signal infor-
mation from the input waveform. V
CC
-V
EE
is generated by
peak detecting the input signal via the internal bridge rec-
tifier and storing it on external capacitors. COM is gener-
ated by an internal amplifier that maintains PV
CC
-COM =
16.5V.
Signal detection is performed by the internal hysteresis
comparator which senses the polarity of the input signal
as shown in Figure 2. This is accomplished by setting (or
resetting) the comparator only if the input signal exceeds
0.95
V
CC
-V
EE
. In some cases it may be necessary to
add a damping resistor across the transformer secondary
to minimize ringing and eliminate false triggering of the
hysteresis comparator as shown in Figure 3.
UC1727
UC2727
UC3727
Figure 1.
Input Stage & Bipolar Supply
Note 1: Guaranteed by design, but not 100% tested in production.
4
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