參數(shù)資料
型號(hào): U634H256S2C45G1
英文描述: PowerStore 32K x 8 nvSRAM
中文描述: PowerStore 32K的× 8非易失
文件頁(yè)數(shù): 9/15頁(yè)
文件大?。?/td> 229K
代理商: U634H256S2C45G1
U634H256
9
August 15, 2006
STK Control #ML0048
Rev 1.1
u: If the chip enable pulse width is less then t
a(E)
(see READ cycle) but greater than or equal to t
w(E)SR
, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
Ai
E
DQi
Output
t
cR
t
w(E)SR
ADDRESS 1
Software Controlled STORE/RECALL Cycle
t, u, v, w
(E = HIGH after STORE initiation)
ADDRESS 6
t
cR
(29)
(29)
t
h(A)SR
(35)
(34)
t
su(A)SR
(33)
Ai
E
DQi
Output
t
cR
t
w(E)SR
ADDRESS 1
VALID
VALID
ADDRESS 6
t
d(E)S
(31)
(32)
(29)
t
h(A)SR
(35)
(34)
t
su(A)SR
(33)
t
dis(E)SR
(30)
t
h(A)SR
(35)
t
su(A)SR
(33)
t
w(E)SR
t
h(A)SR
(35)
(34)
t
su(A)SR
(33)
(5)
t
dis(E)
Software Controlled STORE/RECALL Cycle
t, u, v, w
(E = LOW after STORE initiation)
t
dis(E)SR
(30)
High Impedance
High Impedance
t
d(E)S
(31)
(32)
VALID
VALID
t
d(E)R
t
d(E)R
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