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參數(shù)資料
| 型號： | U634H256CD1C45 |
| 英文描述： | NVRAM (EEPROM Based) |
| 中文描述： | NVRAM中（EEPROM的基礎(chǔ)） |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 239K |
| 代理商： | U634H256CD1C45 |
4
December 12, 1997
U634H256
SRAM MEMORY OPERATIONS
e:
f:
g:
h:
Parameter guaranteed but not tested.
Device is continuously selected with E and G both LOW.
Address valid prior to or coincident with E transition LOW.
Measured
±
200 mV from steady state output voltage.
DC Characteristics
Symbol
Conditions
C-Type
K-Type
Unit
Min.
Max.
Min.
Max.
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
I
OL
= 4.5 V
=-4 mA
= 8 mA
2.4
0.4
2.4
0.4
V
V
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
OL
= 4.5 V
= 2.4 V
= 0.4 V
8
-4
8
-4
mA
mA
Input Leakage Current
High
Low
I
IH
I
IL
V
CC
V
IH
V
IL
= 5.5 V
= 5.5 V
=
0 V
-1
1
-1
1
μ
A
μ
A
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
I
OHZ
I
OLZ
V
CC
V
OH
V
OL
= 5.5 V
= 5.5 V
=
0 V
-1
1
-1
1
μ
A
μ
A
No.Read Cycle
Symbol
25
35
45
Unit
Alt.
IEC
Min.
Max.
Min.
Max.
Min.
Max.
1 Read Cycle Time
f
t
AVAV
t
cR
25
35
45
ns
2 Address Access Time to Data Valid
g
t
AVQV
t
a(A)
25
35
45
ns
3 Chip Enable Access Time to Data Valid
t
ELQV
t
a(E)
25
35
45
ns
4 Output Enable Access Time to Data Valid
t
GLQV
t
a(G)
10
15
20
ns
5
E HIGH to Output in High-Z
h
t
EHQZ
t
dis(E)
10
13
15
ns
6
G HIGH to Output in High-Z
h
t
GHQZ
t
dis(G)
10
13
15
ns
7
E LOW to Output in Low-Z
t
ELQX
t
en(E)
5
5
5
ns
8
G LOW to Output in Low-Z
t
GLQX
t
en(G)
0
0
0
ns
9 Output Hold Time after Address Change
t
AXQX
t
v(A)
3
3
3
ns
10 Chip Enable to Power Active
e
t
ELICCH
t
PU
0
0
0
ns
11 Chip Disable to Power Standby
d, e
t
EHICCL
t
PD
25
35
45
ns
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|---|---|
| U634H256CD1K25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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| U634H256CD1K45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256CSA35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NOVRAM|32KX8|CMOS|SOP|32PIN|PLASTIC |
| U634H256CSC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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