參數(shù)資料
型號: U634H256BSK25
英文描述: NVRAM (EEPROM Based)
中文描述: NVRAM中(EEPROM的基礎(chǔ))
文件頁數(shù): 5/14頁
文件大?。?/td> 239K
代理商: U634H256BSK25
5
December 12, 1997
U634H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
No.Write Cycle
Symbol
25
35
45
Unit
Alt. #1 Alt. #2
IEC
Min. Max. Min. Max. Min. Max.
12
Write Cycle Time
t
AVAV
t
AVAV
t
cW
25
35
45
ns
13
Write Pulse Width
t
WLWH
t
w(W)
20
25
30
ns
14
Write Pulse Width Setup Time
t
WLEH
t
su(W)
20
25
30
ns
15
Address Setup Time
t
AVWL
t
AVEL
t
su(A)
0
0
0
ns
16
Address Valid to End of Write
t
AVWH
t
AVEH
t
su(A-WH)
20
25
30
ns
17
Chip Enable Setup Time
t
ELWH
t
su(E)
20
25
30
ns
18
Chip Enable to End of Write
t
ELEH
t
w(E)
20
25
30
ns
19
Data Setup Time to End of Write
t
DVWH
t
DVEH
t
su(D)
10
12
15
ns
20
Data Hold Time after End of Write
t
WHDX
t
EHDX
t
h(D)
0
0
0
ns
21
Address Hold after End of Write
t
WHAX
t
EHAX
t
h(A)
0
0
0
ns
22
W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
10
13
15
ns
23
W HIGH to Output in Low-Z
t
WHQX
t
en(W)
5
5
5
ns
t
a(A)
Previous
Output Data
t
cR
Address Valid
t
v(A)
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Ai
1
2
9
Ai
E
G
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Output Data
Valid
High Impedance
I
CC
ACTIVE
STANDBY
t
PD
t
PU
1
3
4
5
7
6
8
10
11
t
a(A)
2
Address Valid
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
DQi
Output
DQi
Output
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