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參數(shù)資料
| 型號： | U634H256BSA35 |
| 英文描述： | NOVRAM|32KX8|CMOS|SOP|32PIN|PLASTIC |
| 中文描述： | NOVRAM | 32KX8 |的CMOS |?？苵 32腳|塑料 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 239K |
| 代理商： | U634H256BSA35 |
11
December 12, 1997
U634H256
Device Operation
The U634H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates In SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below V
. RECALL operations are
automatically initiated upon power up and may also
occur when the V
rises above V
, after a low
power condition. RECALL cycles may also be initiated
by a software sequence.
SRAM READ
The U634H256 performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The
address specified on pins A0 - A14 determines which of
the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of t
. If the READ is initiated
by E or G, the outputs will be valid at t
or at t
,
whichever is later. The data outputs will repeatedly
respond to address changes within the t
access time
without the need for transition on any control input pins,
and will remain valid until another address change or
until E or G is brought HIGH or W or HSB is brought
LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid t
before the end of a W
controlled WRITE or t
su(D)
before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers t
dis(W)
after W goes LOW.
AUTOMATIC STORE
During normal operation, the U634H256 will draw cur-
rent from V
to charge up a capacitor connected to
the V
pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the V
pin drops below V
, the part
will automatically disconnect the V
CAP
pin from V
CCX
and initiate a STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of at least 100
μ
F (
±
20 %)
at 6 V.
Each U634H256 must have its own 100
μ
F capacitor.
Each U634H256 must have a high quality, high fre-
quency bypass capacitor of 0.1
μ
F connected between
V
and V
, using leads and traces that are short as
possible. This capacitor do not replace the normal
expected high frequency bypass capacitor between the
power supply voltage and V
.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
AUTOMATIC RECALL
During power up, an automatic RECALL takes place.
At a low power condition (power supply voltage <
V
) an internal RECALL request may be latched.
As soon as power supply voltage exceeds the sense
voltage of V
, a requested RECALL cycle will
automatically be initiated and will take t
RESTORE
to com-
plete.
If the U634H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 k
resistor should be
connected between W and power supply voltage.
SOFTWARE NONVOLATILE STORE
The U634H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the U634H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
相關PDF資料 |
PDF描述 |
|---|---|
| U634H256BSC25 | PRECISION LOW POWER CMOS DUAL OP-AMPS |
| U634H256BSC35 | NVRAM (EEPROM Based) |
| U634H256BSC45 | NVRAM (EEPROM Based) |
| U634H256BSK25 | NVRAM (EEPROM Based) |
| U634H256BSK35 | NVRAM (EEPROM Based) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| U634H256BSC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSC35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSK25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256BSK35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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