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參數(shù)資料
| 型號： | U634H256BD1C45 |
| 英文描述： | NVRAM (EEPROM Based) |
| 中文描述： | NVRAM中（EEPROM的基礎(chǔ)） |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 239K |
| 代理商： | U634H256BD1C45 |
7
December 12, 1997
U634H256
NONVOLATILE MEMORY OPERATIONS
MODE SELECTION
k:
The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0, 3C1F,
303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and dia-
grams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
I/O state assumes that G
≤
V
. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
l:
n:
o:
t
starts from the time V
rises above V
.
HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U634H256 to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U634H256 HSB pins.
E
W
HSB
A13 - A0
(hex)
Mode
I/O
Power
Notes
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
l
L
L
H
X
Write SRAM
Input Data
Active
L
H
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
L
H
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k
X
X
L
X
STORE/Inhibit
Output High Z
I
CC2
/Standby
m
No.
PowerStorePower Up RECALL/
Hardware Controlled STORE
Symbol
Conditions
Min.
Max.
Unit
Alt.
IEC
24
Power Up RECALL Duration
n, e
t
RESTORE
650
μ
s
25
STORE Cycle Duration
t
HLQX
t
d(H)S
V
CC
> 4.5 V
10
ms
26
HSB Low to Inhibit On
e
t
HLQZ
t
dis(H)S
1
μ
s
27
HSB High to Inhibit Off
e
t
HHQX
t
en(H)S
700
ns
28
External STORE Pulse Width
e
t
HLHX
t
w(H)S
20
ns
HSB Output Low Current
e,o
I
HSBOL
HSB = V
OL
3
mA
HSB Output High Current
e, o
I
HSBOH
HSB = V
IL
5
60
μ
A
Low Voltage Trigger Level
V
SWITCH
4.0
4.5
V
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