參數(shù)資料
型號： TZA1047HL/M3
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64
文件頁數(shù)： 8/69頁
文件大?。?/td> 324K
代理商： TZA1047HL/M3
9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
16 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
If the DC-control loop is used, it provides sufcient headroom to select an additional gain
of 12 dB in the VGA (bit HA = 1). This allows the amplitude of the signal into the lters to
be scaled and optimized, which improves SNR.
The output of the VGA is connected to a lter section that comprises an Equalizer (EQ)
and a Noise Filter (NF), which are controlled by bits KEQ, ENEQ, ENNF and word
BWRF[6:0]. The equalizer has a transfer function He(s) shown by Equation 1.
(1)
This represents a 3rd degree equi-ripple phase lter with a good delay response. The
boost factor k is programmable by control bit KEQ via the I2C-bus. The corner frequency
ω0RF =2 π f0RF is programmable by control word BWRF[6:0]. The equalizer is activated by
control bit ENEQ.
The noise lter is a 3rd-order Butterworth low-pass lter which has a transfer function
Hn(s) shown by equation Equation 2.
(2)
The corner frequency
ω
0RF in this lter is equal to the corner frequency of the equalizer
lter. The noise lter is activated by bit ENNF. To reduce power dissipation, the lters
auxiliary circuits, such as the DACs, are switched off when bit ENNF and bit ENEQ are
both logic 0.
The low-ohmic differential output voltage is produced by a driver stage, where the
externally sourced reference voltage at pin RFREF denes the common mode voltage of
output signals RFP and RFN. The driver stage can be disabled to save power by setting
bit DRVON to logic 0.
A low-power, low-speed mode is anticipated for applications such as slim line notebooks,
where maximum speed is less important than power dissipation. By setting bit 5X, the
output bandwidth is limited to approximately 5
× DVD. Note that the maximum speed of the
output is inuenced by the output load. Therefore it may be possible to use the ‘low
dissipation’ mode up to higher speeds in applications having lower output loads, such as
Magnetic Core Memory (MCM).
To enable testing of the DPD lters, signal dtdtst from the input lter of the DPD circuit can
be routed to the output by setting bit TSTDPD1 to logic 1. Due to the implementation, not
all settings of word GRFR[3:0] or GRFW[3:0] are possible in this mode.
H
e s
()
1k
s
2
ω
0RF
2
---------------
×
–
1
s
2
ω
0RF
2
---------------
α
s
ω
0RF
-------------
×
++
-------------------------------------------------------
1
τ
s
ω
0RF
-------------
×
+
-------------------------------
×
=
H
n s
()
1
s
2
ω
0RF
2
---------------
s
ω
0RF
-------------
++
---------------------------------------------
1
s
ω
0RF
-------------
+
----------------------
×
=
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