參數(shù)資料
型號: TWL2214CAPFB
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝: PLASTIC, TQFP-48
文件頁數(shù): 7/39頁
文件大?。?/td> 583K
代理商: TWL2214CAPFB
TWL2214CA
POWER SUPPLY MANAGEMENT IC AND
LiIon BATTERY CHARGE CONTROL
SLVS321A – OCTOBER 2001 – REVISED JANUARY 2002
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SPI bus protocols
The TWL2214CA serial bus is SPI-compatible when a negative transition is generated on the CE input (A8) in
the GQE package.
Unlike I2C, in this mode, the slave device does not send an acknowledge bit for all data received. The data frame
includes 2 start bits, 1 byte of slave address, 1 byte of register address, 1 byte of data, and half clock cycle of
hold time. The total frame length, therefore, includes 26 full clock cycles and the rising edge of the 27th clock
cycle. After the rising edge of the 27th clock cycle, CLK remains high.
The following requirements must be satisfied for the interface:
1.
CE goes low after the falling edge of CLK and remains low for no longer than 35 clock cycles. The data line
must remain unchanged prior to the initial trailing edge of the CLK line. Failure to comply triggers the I2C
start condition and the SPI interface fails.
2.
Input data is sampled on the rising edge of the CLK when CE is set to low.
3.
Input data is latched into the device on the last (26th) rising edge of the CLK.
4.
If CE goes high before completing the transmission, data is ignored and the register is not updated.
5.
Output data is updated on the falling edge of the CLK when CE is set to low.
6.
The first two bits in the data line are dead bits to allow enough time for the communication mode option
selection of the SPI.
7.
During a read operation the direction of data line changes after the register address is received.
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