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參數(shù)資料
| 型號： | TWL1103TPBSRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
| 封裝： | PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 458K |
| 代理商： | TWL1103TPBSRQ1 |
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TWL1103T Q1
VOICEBAND AUDIO PROCESSOR (VBAP)
SGLS120B APRIL 2002 REVISED APRIL 2008
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, VDD = 2.7 V, TA = 40°C to 105°C (unless otherwise noted) (continued)
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage rejection, transmit channel
MIC1N, MIC1P =0 V,
VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz
80
45
dB
Supply voltage rejection, receive channel,
EAR1 selected (differential)
PCM code = positive zero,
VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz
90
45
dB
Crosstalk attenuation, transmit-to-receive
(differential)
MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured
differentially between EAR1ON and EAR1OP
70
dB
Crosstalk attenuation, receive-to-transmit
PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at
PCMO, EAR1 amplifier
70
dB
DTMF generator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DTMF high to low tone relative amplitude
(preemphasis)
1.5
2
2.5
dB
MICBIAS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Load impedance
2.0
2.5
k
timing requirements
clock
MIN
NOM
MAX
UNIT
tt
Transition time, MCLK
10
ns
MCLK frequency
2.048
MHz
MCLK jitter
37%
Number of PCMCLK clock cycles per PCMSYN frame
256
tc(PCMCLK) PCMCLK clock period
156
488
512
ns
Duty cycle, PCMCLK
45%
50%
68%
transmit (see Figure 6)
MIN
MAX
UNIT
tsu(PCMSYN)
Setup time, PCMSYN high before PCMCLK
↓
20
tc(PCMCLK)20
ns
th(PCMSYN)
Hold time, PCMSYN high after PCMCLK
↓
20
tc(PCMCLK)20
ns
receive (see Figure 5)
MIN
MAX
UNIT
tsu(PCSYN)
Setup time, PCMSYN high before PCMCLK
↓
20
tc(PCMCLK)20
ns
th(PCSYN)
Hold time, PCMSYN high after PCMCLK
↓
20
tc(PCMCLK)20
ns
tsu(PCMI)
Setup time, PCMI high or low before PCMCLK
↓
20
ns
th(PCMI)
Hold time, PCMI high or low after PCMCLK
↓
20
ns
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