參數(shù)資料
型號(hào): TWL1101PFBR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, TQFP-48
文件頁(yè)數(shù): 6/31頁(yè)
文件大小: 408K
代理商: TWL1101PFBR
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS074A – MAY 1998 REVISED MARCH 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Receive noise, C-message weighted
PCMIN = 0000000000000
106
Vrms
PCMIN to EAR2O at 3 dBm0
24
dB
PCMIN to EAR2O at 0 dBm0
45
dB
PCMIN to EAR2O at –5 dBm0
44
dB
Receive signal to distortion ratio with 1020 Hz sine wave input
PCMIN to EAR2O at –10 dBm0
42
dB
Receive signal-to-distortion ratio with 1020-Hz sine-wave input
PCMIN to EAR2O at –20 dBm0
39
dB
PCMIN to EAR2O at –30 dBm0
32
dB
PCMIN to EAR2O at –40 dBm0
20
dB
PCMIN to EAR2O at –45 dBm0
16
dB
Intermodulation distortion, 2-tone CCITT method, composite power
level, –13 dBm0
CCITT G.712 (7.1), R2
50
dB
Intermodulation distortion, 2-tone CCITT method, composite power
level, –13 dBm0
CCITT G.712 (7.2), R2
54
dB
NOTE 7: RXPGA = 0 dB, RXVOL = 0 dB
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage rejection, transmit channel
MIC1N, MIC1P =0 V, VDD = 3 Vdc + 100 mVrms,
f = 0 –30 KHz
–45
–50
dB
Supply voltage rejection, receive channel
PCM code = positive zero, VDD = 3 Vdc + 100 mVrms,
f = 0 –30 KHz
–45
–50
dB
Crosstalk attentuation, transmit-to-receive
(differential)
MIC1N, MIC1P = 0 dB, f = 300 – 3400 Hz measured
differentially between EAR1ON and EAR1OP
70
dB
Crosstalk attenuation, receive-to-transmit
PCMIN = 0 dBm0, f = 300 – 3400 Hz measured at
PCMO, EAR1 amplifier unloaded
70
dB
clock timing requirements
PARAMETER
MIN
NOM
MAX
UNIT
tt
Transition time, MCLK
10
ns
fmclk
MCLK frequency
2.048
2.5
MHz
MCLK jitter
37
%
Number of MCLK clock cycles per PCMSYN frame
256
tc(PCMCLK) PCMCLK clock period
156
488
512
ns
Duty cycle, PCMCLK
45
50
68%
transmit timing requirements (see Figure 6)
PARAMETER
MIN
MAX
UNIT
tsu(PCMSYN)
Setup time, PCMSYN high before falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
th(PCMSYN)
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
receive timing requirements (see Figure 7)
PARAMETER
MIN
MAX
UNIT
tsu(PCSYN)
Setup time, PCMSYN high before falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
th(PCSYN)
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
tsu(PCMI)
Setup time, PCMI high or low before falling edge of PCMCLK
20
ns
th(PCMI)
Hold time, PCMI high or low after falling edge of PCMCLK
20
ns
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