TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS074A – MAY 1998 REVISED MARCH 1999
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
I2C–bus protocol
The VBAP serial interface is designed to be I2C-bus compatible. This interface consists of the following
terminals:
SCL: I2C-bus serial clock – This input synchronizes the data transfer from and to the codec.
SDA: I2C-bus serial address/data input/output – This is a bidirectional pin that transfers register control
addresses and data into and out of the codec. It is an open drain terminal and therefore requires a
pullup resistor to VCC (typical 10 k for 100 KHz).
TWL1101 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode.
For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are
reserved for indicating the start and stop conditions.
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted
as a start or stop condition.
Table 7. I2C-Bus Conditions
CONDITION
STATUS
DESCRIPTION
A
Bus not busy
Both data and clock lines remain at high
B
Start data transfer
A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
C
Stop data transfer
A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
D
Data valid
The state of the data line represents valid data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal.
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit data.
Each data transfer is initiated with a start condition and terminated with a stop condition. No consecutive stop
and start conditions are allowed in a single clock high period (see Figure 4). The number of data bytes
transferred between the start and stop conditions is determined by the master device.
When addressed, the VBAP generates an acknowledge after the reception of each byte. The master device
(microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit.
The VBAP must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
into account. During read operations, a master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (VBAP) must leave
the data line high to enable the master to generate the stop condition.
current reference
An external current setting resistance of 100 k
±1% must be connected from REXT to ground. No capacitance
should be connected to this pin, and stray capacitance should be minimized.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 KHz determines the sampling rate.