參數(shù)資料
型號(hào)： TVP5158IPNPR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： GREEN, PLASTIC, HTQFP-128
文件頁(yè)數(shù)： 95/108頁(yè)
文件大?。?/td> 1395K
代理商： TVP5158IPNPR
SLES243E
– JULY 2009 – REVISED MARCH 2011
Table 4-93. Interrupt Clear
Subaddress
F6h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Sig_Present
Weak_Sig
Vid_Lock
Macrovision
Vid_Std
Reserved
The host interrupt Clear register is used by the external processor to clear the interrupt status bits in the host interrupt status register. When
no non-masked interrupts remain set in the register, the external interrupt pin also becomes inactive.
Sig_Present
Signal present interrupt clear
0
No effect (default)
1
Clear interrupt bit
Weak_Sig
Weak signal interrupt clear
0
No effect (default)
1
Clear interrupt bit
Vid_Lock
Video (HV) lock change interrupt clear
0
No effect (default)
1
Clear interrupt bit
Macrovision
Macrovision change interrupt clear
0
No effect (default)
1
Clear interrupt bit
Vid_Std
Video standard change interrupt clear
0
No effect (default)
1
Clear interrupt bit
Table 4-94. Decoder Write Enable
Subaddress
FEh
Default
0Fh
7
6
5
4
3
2
1
0
Decoder Auto
Reserved
Addr Auto Incr
Decoder 4
Decoder 3
Decoder 2
Decoder 1
Incr
This register controls which of the four decoder cores receives I2C write transactions. A 1 in the corresponding Decoder bit will enable the
decoder to receive write commands. Any combination of decoders can be configured to receive write commands, allowing all four decoders
to be programmed concurrently.
The following table shows how the address auto-increment and decoder auto-increment functions operate when a multi-byte I2C write
transaction occurs. For this example, decoders 2, 3 and 4 are enabled for writes, the sub-address is 0xA0 and 8 bytes of data are written.
Decoder Auto Incr
0
1
Addr Auto Incr
0
1
0
1
Data
Dec
Addr
Dec
Addr
Dec
Addr
Dec
Addr
1st
2,3,4
A0
2,3,4
A0
2
A0
2
A0
2nd
2,3,4
A0
2,3,4
A1
3
A0
3
A0
3rd
2,3,4
A0
2,3,4
A2
4
A0
4
A0
4th
2,3,4
A0
2,3,4
A3
2
A0
2
A1
5th
2,3,4
A0
2,3,4
A4
3
A0
3
A1
6th
2,3,4
A0
2,3,4
A5
4
A0
4
A1
7th
2,3,4
A0
2,3,4
A6
2
A0
2
A2
8th
2,3,4
A0
2,3,4
A7
3
A0
3
A2
Copyright
2009–2011, Texas Instruments Incorporated
Internal Control Registers
87
Product Folder Link(s): TVP5158 TVP5157 TVP5156
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