參數(shù)資料
型號： TVP5154APNPR
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： GREEN, PLASTIC, HTQFP-128
文件頁數(shù)： 78/92頁
文件大小： 1089K
代理商： TVP5154APNPR
SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
www.ti.com
TERMINAL
I/O
DESCRIPTION
NAME
NO.
HSYNC1
100
HSYNC2
77
O
Horizontal synchronization
HSYNC3
58
HSYNC4
39
VSYNC1/PALI1
95
1.
VSYNC: Vertical synchronization
VSYNC2/PALI2
76
O
2.
PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator, a 1
VSYNC3/PALI3
57
indicates a noninverted line, and a 0 indicates an inverted line.
VSYNC4/PALI4
38
Power down (active low). A 0 on this pin puts the decoder in standby mode. PDN preserves
PDN
122
I
the value of the registers.
Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it
RESETB
121
I
resets all the registers and restarts the internal microprocessor.
SCL
120
I/O
I2C serial clock (open drain)
SDA
119
I/O
I2C serial data (open drain)
During power-on reset, this pin is sampled along with pin 117 (I2CA1) to determine the I2C
I2CA0
118
I
address the device is configured to. A 10-k
resistor should pull this either high (to IOVDD)
or low to select different I2C device addresses.
During power-on reset, this pin is sampled along with pin 118 (I2CA0) to determine the I2C
I2CA1
117
I
address the device is configured to. A 10-k
resistor should pull this either high (to IOVDD)
or low to select different I2C device addresses.
CLK1
103
CLK2
84
O
Unscaled system data clock at either 27 MHz or 54 MHz
CLK3
61
CLK4
42
SCLK1
104
SCLK2
85
Scaled system data clock at 27 MHz. This signal can be used to qualify scaled/unscaled
O
SCLK3
62
data when the unscaled system data clock is set to 54 MHz.
SCLK4
43
External clock reference. The user may connect XIN to an oscillator or to one terminal of a
XIN/OSC
124
I
crystal oscillator. The user may connect XOUT to the other terminal of the crystal oscillator
XOUT
123
O
or not connect XOUT at all. One single 14.31818-MHz crystal or oscillator is needed for
ITU-R BT.601 sampling, for all supported standards.
CH1_OUT[7:0]
105–112
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 1
CH2_OUT[7:0]
86–93
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 2
CH3_OUT[7:0]
67–74
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 3
CH4_OUT[7:0]
48–55
O
Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 4
Test-mode select. This pin should be connected to digital ground for correct device
TMS
36
I
operation.
8
Device Details
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TVP5154A
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參數(shù)描述
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TVP5154PNPR 功能描述:視頻 IC 4Ch Lo Pwr PAL/NTSC SECAM Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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