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SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
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I
2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. The input pins I2CA0 and
I2CA1 are used to select the slave address to which the device responds. Although the I2C system can be
multimastered, the TVP5154A decoder functions as a slave device only.
Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are
high. The slave address select terminals (I2CA0 and I2CA1) enable the use of four TVP5154A decoders
on the same I2C bus. At the trailing edge of reset, the status of the I2CA0 and I2CA1 lines are sampled to
determine the device address used. Table 4-1 summarizes the terminal functions of the I2C-mode host interface.
Table 4-2 shows the device address selection options.
Table 4-1. I2C Terminal Description
SIGNAL
TYPE
DESCRIPTION
I2CA0
I
Slave address selection
I2CA1
I
Slave address selection
SCL
I/O (open drain)
Input/output clock line
SDA
I/O (open drain)
Input/output data line
Table 4-2. I2C Host Interface Device Addresses
A6
A5
A4
A3
A2
A1 (I2CA1)
A0 (I2CA0)
R/W
HEX
1
0
1
0
1/0
B9/B8
1
0
1
0
1
1/0
BB/BA
1
0
1
0
1/0
BD/BC
1
0
1
1/0
BF/BE
Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL, except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be eight bits long. The number of bytes that can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
To simplify programming of each of the four decoder channels, a single I2C write transaction can be
transmitted to any one or more of the four cores in parallel. This reduces the time required to download
firmware or to configure the device when all channels are to be configured in the same manner. It also
enables the addresses for all registers to be common across all decoders.
I2C sub-address 0xFE contains four bits, with each bit corresponding to one of the decoder cores. If this
bit is set, I2C write transactions are sent to the corresponding decoder core. If the bit is 0, the
corresponding decoder does not receive the I2C write transactions.
I2C sub-address 0xFF contains four bits, with each bit corresponding to one of the decoder cores. If this
bit is set, I2C read transactions are sent to the corresponding decoder core. Note, only one of the bits in
this register should be set at a given time, ensuring that only one decoder core is accessed at a time for
read operations. If more than one bit is set, the lowest set bit number corresponds to the core that
responds to the read transaction.
Note that, when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when
register 0xFF is written to with any value, register 0xFE is set to 0x00.
Copyright 2007–2010, Texas Instruments Incorporated
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I2C Host Interface