參數(shù)資料
型號(hào)： TVP5151ZQCR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PBGA48
封裝： GREEN, PLASTIC, BGA-48
文件頁(yè)數(shù)： 14/85頁(yè)
文件大小： 958K
代理商： TVP5151ZQCR
5
XTAL1/OSC
27.000-MHz
Crystal
CL1
CL2
XTAL2
6
R
TVP5151
CLK_IN
NC
26
IO_DVDD
10
5
XTAL1/OSC
XTAL2
6
TVP5151
CLK_IN
NC
26
IO_DVDD
10
1.8 V to 3.3 V
27.000-MHz
1.8-V Clock
5
XTAL1/OSC
XTAL2
6
TVP5151
CLK_IN
26
IO_DVDD
10
27.000-MHz
1.8-V to 3.3-V
Clock
NC
1.8 V to 3.3 V
TVP5151
www.ti.com
SLES241D – SEPTEMBER 2009 – REVISED MARCH 2011
3.15.2.3 I2C Timing Requirements
The TVP5151 decoder requires delays in the I2C accesses to accommodate its internal processor's timing.
In accordance with I2C specifications, the TVP5151 decoder holds the I2C clock line (SCL) low to indicate
the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low
condition, then the maximum delays must always be inserted where required. These delays are of variable
length; maximum delays are indicated in the following diagram:
Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays).
Slave
Start
address
Ack
Subaddress
Ack
Data (XXh)
Ack
Wait 64 s
Stop
(B8h)
The 64-s delay is for all registers that do not require a reinitialization. Delays may be more for some
registers.
3.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 27.000-MHz clock is required to
drive the PLL. This may be input to the TVP5151 decoder on terminal 5 (XTAL1), or a crystal of
27.000-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2).
Figure 3-8 shows the reference clock configurations. For the example crystal circuit shown (a
parallel-resonant crystal with 27.000-MHz fundamental frequency), the external capacitors must have the
following relationship:
CL1 = CL2 = 2CL – CSTRAY
where CSTRAY is the terminal capacitance with respect to ground, and CL is the crystal load capacitance
specified by the crystal manufacturer.
Figure 3-8 shows the reference clock configurations.
NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-k
Ω resistor
may be used for most crystal types.
Figure 3-8. Reference Clock Configurations
An alternate method to supply an external source with a 1.8-V to 3.3-V peak-to-peak level is to pull pin 5
(XTAL1/OSC) low and connect a 1.8-V to 3.3-V external oscillator clock source to pin 26, AVID/CLK_IN,
depending on what IO_DVDD supply voltage is used.
Clock source frequency should have an accuracy of ±50 ppm (max).
Copyright 2009–2011, Texas Instruments Incorporated
Functional Description
21
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