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參數(shù)資料
| 型號(hào)： | TVP5150PBSRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP32 |
| 封裝： | GREEN, PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大小： | 453K |
| 代理商： | TVP5150PBSRG4 |
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Detailed Description
5
SLES043 — September 2002
TVP5150
Table 1–1. Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
DIGITAL SECTION (CONTINUED)
INTREQ/GPCL
27
I/O
INTREQ: interrupt request.
GPCL: General-purpose control logic. This terminal has three functions:
1.
General-purpose output. In this mode the state of GPCL is directly programmed via the host port.
2.
Vertical blank output. In this mode the GPCL terminal is used to indicate the vertical blanking interval
of the output video. The beginning and end times of this signal are programmable via the host port
control.
3.
Sync lock control input. In this mode when GPCL is high, the output clock frequencies and the sync
timing are forced to nominal values.
IO_DVDD
10
I
IO digital supply. Either 1.8 V or 3.3 V depending on requirements.
PDN
28
I
Power-down pin. Puts device in standby mode. Preserves the value of the registers, but PLL, analog
channel, and all the digital circuitry are shut down.
SCAN
8
Scan test input
SCL
21
I/O
I2C serial clock
SCLK/PCLK
9
O
System clock outputs with twice the frequency of the pixel clock (PCLK). Pixel clock for the data
SDA
22
I/O
I2C serial data
VSYNC/PALI
24
O
VSYNC: vertical synchronization
PALI: PAL line indicator or horizontal lock indicator.
For PAL line indicator, a logic 1 indicates a noninverted line, and a logic 0 indicates an inverted line.
XTAL1/OSC
XTAL2
5
6
I
External clock reference. The user may connect XTAL1 to a TTL-compatible oscillator or to one terminal of a
crystal oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for square pixel sampling and ITU-R
BT.601 sampling.
YOUT(6:0)*
12–18
O
Output decoded ITU-R BT656 output/YUV 422 output.
YOUT(7)/I2CSEL
11
I/O
I2CSEL: Determines address for I2C (sampled at startup)
Logic 1: Address = xxH, Logic 0: Address: yyH
YOUT7: MSB of Output decoded ITU-R BT656 output/YUV 422 output.
2
Detailed Description
2.1
Input Multiplexers and Buffers
The TVP5150 has an analog input channel that can accept two CVBS video inputs, ac-coupled through 0.1-
F
capacitors. The two analog input ports can be connected as follows.
Two selectable composite video inputs
One S-video input
The internal video multiplexers can be configured via the host port. The internal nodes are grounded for zero
channel crosstalk. The input buffers are continuous time amplifiers, which allow an input range of up to 0.75 V.
This allows the decoder to support input ranges of 0.5 V to 1.5 V with an input attenuation of 1/2. The selection
is done by register settings.
2.2
Clamp
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit
provides line-by-line restoration of the video sync level to a fixed dc reference voltage. Two modes of clamping
are provided, coarse and fine.
In coarse mode, the most negative portion of the input signal (typically the sync tip) is clamped to a fixed
dc level and remains on. Typically, this level is the sync tip. This mode is used while the timing processor
is searching for the horizontal sync.
Fine clamp mode is enabled after the horizontal lock is achieved. This is enabled to prevent spurious level
shifting caused by noise more negative than the sync tip on the input signal. If fine clamp mode is selected,
clamping is only enabled during the sync period.
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