
Functional Description
34
May 2006
SLES043A
Detailed timing information is also available in Section 3.15, Synchronization Signals.
3.22.23 Vertical Blanking Start Register
Address
18h
7
6
5
4
3
2
1
0
Vertical blanking start
Vertical blanking (VBLK) start:
0111 1111 = 127 lines after start of vertical blanking interval
0000 0001 = 1 line after start of vertical blanking interval
0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 39)
1000 0001 = 1 line before start of vertical blanking interval
1111 1111 = 128 lines before start of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
register determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
register 03h). The setting in this register also determines the duration of the luma bypass function (see register
07h).
3.22.24 Vertical Blanking Stop Register
Address
19h
7
6
5
4
3
2
1
0
Vertical blanking stop
Vertical blanking (VBLK) stop:
0111 1111 = 127 lines after stop of vertical blanking interval
0000 0001 = 1 line after stop of vertical blanking interval
0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 39)
1000 0001 = 1 line before stop of vertical blanking interval
1111 1111 = 128 lines before stop of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
register determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
register 03h). The setting in this register also determines the duration of the luma bypass function (see register
07h).
3.22.25 Chrominance Control #1 Register
Address
1Ah
7
6
5
4
3
2
1
0
Reserved
Color PLL reset
Chrominance adaptive
comb filter enable (ACE)
Chrominance comb filter
enable (CE)
Automatic color gain control
Color PLL reset:
0 = Color PLL not reset (default)
1 = Color PLL reset
Color PLL phase is reset to zero and the color PLL reset bit then immediately returns to zero. When this bit
is set, the subcarrier PLL phase reset bit is transmitted on terminal 23 (GLCO) on the next line (NTSC or PAL).
Chrominance adaptive comb filter enable (ACE):