參數(shù)資料
型號(hào): TVP5150AM1ZQC
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PBGA48
封裝: GREEN, PLASTIC, BGA-48
文件頁數(shù): 17/88頁
文件大?。?/td> 997K
代理商: TVP5150AM1ZQC
RTC
M
S
B
16 CLK
L
S
B
21
0
128 CLK
22-Bit Fsc Frequency Control
Start
Bit
Reset
Bit
2 CLK
1 CLK
2 CLK
3 CLK
1 CLK
PAL
Switch
44 CLK
SLES209D – NOVEMBER 2007 – REVISED SEPTEMBER 2010
www.ti.com
3.17.2 RTC Mode
Figure 3-10 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower
than the GLCO clock rate. For Color PLL frequency control, the upper 22 bits are used. Each frequency
control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the
last bit of PLL frequency control.
Figure 3-10. RTC Timing
3.18 Reset and Power Down
The RESETB and PDN terminals work together to put the TVP5150AM1 decoder into one of the two
modes. Table 3-8 shows the configuration.
After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB
signal as depicted in Figure 3-11. After RESETB is released, the data (YOUT0 to YOUT7) and sync
(HSYNC, VSYNC/PALI) outputs are in high-impedance state until the TVP5150AM1 is initialized and the
outputs are activated.
NOTE
I
2C SCL and SDA signals must not change state until the TVP5150AM1 reset sequence has
been completed.
Table 3-8. Reset and Power-Down Modes
PDN
RESETB
CONFIGURATION
0
Reserved (unknown state)
0
1
Powers down the decoder
1
0
Resets the decoder
1
Normal operation
24
Functional Description
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): TVP5150AM1
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