參數(shù)資料
型號: TVP5147M1IPFPQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: PLASTIC, HTQFP-80
文件頁數(shù): 93/108頁
文件大?。?/td> 937K
代理商: TVP5147M1IPFPQ1
www.ti.com
SLES140F – JULY 2005 – REVISED DECEMBER 2010
Table 2-110. Interrupt Clear 0 Register
Subaddress
F6h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
The host Interrupt Clear 0 and Interrupt Clear 1 registers are used by the external processor to clear the interrupt status bits in the host
Interrupt Status 0 and Interrupt Status 1 registers. When no nonmasked interrupts remain set in the registers, the external interrupt terminal
also becomes inactive.
FIFO THRS:
FIFO threshold passed clear
0 = No effect (default)
1 = Clear FIFO_THRES bit in status register 0 bit 7
TTX:
Teletext data available clear
0 = No effect (default)
1 = Clear TTX available bit in status register 0 bit 6
WSS/CGMS:
WSS/CGMS data available clear
0 = No effect (default)
1 = Clear WSS/CGMS available bit in status register 0 bit 5
VPS/Gemstar:
VPS/Gemstar data available clear
0 = No effect (default)
1 = Clear VPS/Gemstar available bit in status register 0 bit 4
VITC:
VITC data available clear
0 = Disabled (default)
1 = Clear VITC available bit in status register 0 bit 3
CC F2:
CC field 2 data available clear
0 = Disabled (default)
1 = Clear CC field 2 available bit in status register 0 bit 2
CC F1:
CC field 1 data available clear
0 = Disabled (default)
1 = Clear CC field 1 available bit in status register 0 bit 1
LINE:
Line number interrupt clear
0 = Disabled (default)
1 = Clear Line interrupt available bit in status register 0 bit 0
Copyright 2005–2010, Texas Instruments Incorporated
Functional Description
85
Product Folder Link(s): TVP5147M1
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