參數(shù)資料
型號(hào)： TVP5146PFPRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： PLASTIC, HTQFP-80
文件頁(yè)數(shù)： 34/106頁(yè)
文件大小： 1500K
代理商： TVP5146PFPRG4
25
SLES084C August 2007
TVP5146
Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not
driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on
the board. The slave-address select signal, terminal 37 (I2CA), enables the use of two TVP5146
decoders tied to the same I2C bus by controlling the least significant bit of the I2C device
address.
Table 24. I2C Host Interface Terminal Description
SIGNAL
TYPE
DESCRIPTION
I2CA
I
Slave address selection
SCL
I
Input clock line
SDA
I/O
Input/output data line
2.6.1 Reset and I2C Bus Address Selection
The TVP5146 decoder can respond to two possible chip addresses. The address selection is
made at reset by an externally supplied level on the I2CA terminal. The TVP5146 decoder
samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures
the I2C bus address bit A0. The I2CA terminal has an internal pulldown resistor to pull the
terminal low to set a zero.
Table 25. I2C Address Selection
A6
A5
A4
A3
A2
A1
A0 (I2CA)
R/W
HEX
1
0
1
0
0 (default)
1/0
B9/B8
1
0
1
0
1
1/0
BB/BA
If terminal 37 is strapped to DVDD via a 2.2-k resistor, I2C device address A0 is set to 1.
2.6.2 I2C Operation
S
1011 1000
ACK
Subaddress
ACK
Send data
ACK
P
Data transfers occur using the following illustrated formats.
Read from I2C control registers
S
1011 1000
ACK
Subaddress
ACK
S
1011 1001
ACK
Receive data
NAK
P
S = I2C bus start condition
P = I2C bus stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple-byte read master with ACK for each byte except
last byte
Subaddrress = Subaddress byte
Data = Data byte, if more than one byte of data is transmitted (read and write), the subaddress pointer is
automatically incremented.
I2C bus address = Example showing that I2CA is in default mode. Write (B8h), read (B9h)
2.6.3 VBUS Access
The TVP5146 decoder has additional internal registers accessible through an indirect access to
an internal 24-bit address wide VBUS. Figure 225 shows the VBUS registers access.
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