參數(shù)資料
型號(hào): TVP5146PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: GREEN, PLASTIC, HTQFP-80
文件頁(yè)數(shù): 20/109頁(yè)
文件大?。?/td> 1658K
代理商: TVP5146PFP
10
SLES084C August 2007
TVP5146
2.1.2 Analog Input Clamping
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The
clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference
voltage. The selection between bottom and mid clamp is performed automatically by the
TVP5146 decoder.
2.1.3 Automatic Gain Control
The TVP5146 decoder uses four programmable gain amplifiers (PGAs), one per channel. The
PGA can scale a signal with a voltage-input compliance of 0.5-VPP to 2-VPP to a full-scale 10-bit
A/D output code range. A 4-bit code sets the coarse gain with individual adjustment per channel.
Minimum gain corresponds to a code 0x0 (2-VPP full-scale input, –6-dB gain) while maximum
gain corresponds to code 0xF (0.5 VPP full scale, +6-dB gain). The TVP5146 decoder also has
12-bit fine gain controls for each channel and applies independently to coarse gain controls. For
composite video, the input video signal amplitude can vary significantly from the nominal level of
1 VPP. The TVP5146 decoder can adjust its PGA setting automatically: an AGC can be enabled
and can adjust the signal amplitude such that the maximum range of the ADC is reached without
clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In
these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the
TVP5146 decoder can read the gain currently being used.
The TVP5146 AGC comprises the front-end AGC before Y/C separation and the back-end AGC
after Y/C separation. The back-end AGC restores the optimum system gain whenever an
amplitude reference such as the composite peak (which is only relevant before Y/C separation)
forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms
can use up to four amplitude references: sync height, color burst amplitude, composite peak,
and luma peak.
The specific amplitude references being used by the front-end and back-end AGC algorithms
can be independently controlled using the AGC white peak processing register located at
subaddress 74h. The TVP5146 gain increment speed and gain increment delay can be
controlled using the AGC increment speed register located at subaddress 78h and the AGC
increment delay register located at subaddress 79h, respectively.
2.1.4 Analog-to-Digital Converters (ADCs)
All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive
an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and
30 MHz. All ADC reference voltages are generated internally.
2.2
Digital Video Processing
Figure 22 is a block diagram of the TVP5146 digital video decoder processor. This processor
receives digitized video signals from the ADCs and performs composite processing for CVBS
and S-video inputs, YCbCr signal enhancements for CVBS and S-video inputs, and YPbPr/RGB
processing for component video inputs. It also generates horizontal and vertical syncs and other
output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide
field identification, horizontal and vertical lock, vertical blanking, and active video window
indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with
external syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync
pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material.
Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656
output as ancillary data or stored in internal FIFO and/or registers for retrieval via the host port
interface.
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