2–14
2.4
Genlock Control
The frequency control word of the internal color subcarrier digital control oscillator (DCO) and the subcarrier
phase reset bit are transmitted via the GLCO terminal. The frequency control word is a 23-bit binary number.
The frequency of the DCO can be calculated from the following equation:
F
dco +
F
ctrl
223
× F
sclk
Where Fdco is the frequency of the DCO, Fctrl is the 23-bit DCO frequency control, and Fsclk is the frequency
of the SCLK.
The last bit (bit 0) of the DCO frequency control is always 0.
A write of 1 to bit 4 of the chrominance control register at host port subaddress 1Ah causes the subcarrier
DTO phase reset bit to be sent on the next scan line on GLCO. The active low reset bit occurs 8 SCLKs after
the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the phase
of the TVP5010 internal subcarrier DCO is reset to zero.
A genlocking slave device connected to the GLCO terminal can use the information on GLCO to synchronize
its internal color phase DCO to achieve clean line and color lock.
Figure 2–13 shows the timing of GLCO.
SCLK
GLCO
23-Bit frequency control
Start bit
DCO reset
MSB
LSB
>128 SCLK
1
SCLK
1
SCLK
8 SCLK
23 SCLK
Figure 2–13. GLCO Timing
2.5
Video Port Timing/Formatting
Applying the control signal to the OEB terminal and/or via host port control activates the YUV data outputs
or sets them to high–impedance. When the host configures OEB to control the YUV outputs, then a logic
0 on OEB enables the output and a logic 1 puts the YUV output bus in a high impedance state. Alternately,
OEB can be tied to ground and host port bus alone controls the YUV terminals. Figure 2–14 shows digital
outputs, YUV, and the clock and control timing with OEB as the output control. PCLK and SCLK are the pixel
clock and the system clock respectively. The active video indicator (AVID) signal defines which pixels in each
horizontal video line contain picture information.