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參數(shù)資料
| 型號(hào)： | TVP3703-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（雙鎖相環(huán)，先進(jìn)的視頻接口調(diào)色器） |
| 文件頁(yè)數(shù)： | 12/21頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | TVP3703-135 |
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TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
pixel port (continued)
Table 6. Extended Pixel Modes
SVGA MODE
PIXEL WORD
LATCHED
USE OF PIXEL INPUT TERMINALS
P15
X
P14
X
P13
X
P12
X
P11
X
P10
X
P9
X
P8
X
P7
P7
P6
P6
P5
P5
P4
P4
P3
P3
P2
P2
P1
P1
P0
P0
00h
8-bit indexed
single P(7–0)
01h
15-bit mixed
single P(15–0)
0
or
1
X
R7
X
R6
X
R5
X
R4
X
R3
X
G7
X
G6
P7
G5
P6
G4
P5
G3
P4
B7
P3
B6
P2
B5
P1
B4
P0
B3
02h
15-bit direct
single P(15–0)
X
R7
R6
R5
F4
F3
G7
G6
G5
G4
G3
B7
B6
B5
B4
B3
03h
16-bit direct
single P(15–0)
R7
R6
R5
R4
R3
G7
G6
G5
G4
G3
G2
B7
B6
B5
B4
B3
04h
24-bit direct
first P(15–0)
second P(15–0)
G7
X
G6
X
G5
X
G4
X
G3
X
G2
X
G1
X
G0
X
B7
R7
B6
R6
B5
R5
B4
R4
B3
R3
B2
R2
B1
R1
B0
R0
05h
Double 8-bit
i d
indexed,§
d §
single P(15–0)
P7
P6
P5
P4
P3
P2
P1
P0
P7
6
P5
P4
P3
P2
P1
P0
second displayed pixel
first displayed pixel
06h
16-bit direct
(5–6–5)
first P(7–0)
second P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
G4
R7
G3
R6
G2
R5
B7
R4
B6
R3
B5
G7
B4
G6
B3
G5
07h
8-bit indexed
first P(3–0)
second P(3–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P3
P7
P2
P6
P1
P5
P0
P4
08h
15-bit direct
(5–5–5)
first P(7–0)
second P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
G5
X
G4
R7
G3
R6
B7
R5
B6
R4
B5
R3
B4
G7
B3
G6
09h
Double 24-bit
direct§
first P(15–0)
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
first displayed pixel
second P(15–0)
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
R4
R3
R2
R1
R0
second displayed pixel
third P(15–0)
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
Pipe delay for mode = 3 PCLK + 7 dot clocks
Unspecified bits = 0
§Modes 5 (05h) and 9 (09h) use PLL, DAC CLK = 2
×
PCLK or 2/3 PCLK respectively.
primary and secondary pixel mode combinations
Writing to the pixel command register enables the extended pixel modes. A primary pixel mode and a secondary
pixel mode are defined for the TVP3703. The TVP3703 switches between these two modes on the fly under
control of the PIXMIX terminal.
The PIXMIX terminal and the pixel terminals are sampled on PCLK. If the primary or secondary pixel mode
format requires two PCLK edges to build a whole pixel, then PIXMIX should only change state on every second
PCLK edge after BLANK has gone high at the start of a line.
When PIXMIX is not in use, the primary and secondary pixel mode select registers should be written with the
same value.
The primary and secondary pixel mode combinations are listed in Table 7.
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