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參數(shù)資料
| 型號： | TVP3409-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| 中文描述： | 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS） |
| 文件頁數(shù)： | 20/57頁 |
| 文件大小： | 312K |
| 代理商： | TVP3409-170 |
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2–8
2.2.9
The clock synthesizer control register is written to or read by the MPU and it is not initialized at power on.
Table 2–10 defines the bits of the clock synthesizer control register.
Clock Synthesizer Control Register (CC)
CC(0) is the LSB and corresponds to D0 on the MPU port.
CC(7) determines whether the frequency select input terminals FS(1,0) or the clock synthesizer control
register bits CC(5,4) control the frequency selection for clock synthesizer A (PLLA) and OTCLKA.
CC(6) is reserved. This bit can be read which returns the value written, but it does not affect the function
of the device.
CC(3) determines whether the frequency select input terminals FS(1,0) or the clock synthesizer control
register bits CC(1,0) control the frequency selection for clock synthesizer B (PLLB) and OTCLKB.
CC(2) is reserved. This bit can be read which returns the value written, but it does not affect the function
of the device.
This register is operational on power up. It can be read or written to by the MPU at any time and it is not
initialized. All bits are set to zero upon asserting RESET. To read or write this register, set bit CR0(0) = 1,
write 0x06 to the WMA, and set RS(1,0) = 10. This register cannot be accessed by state machine addressing
(see Table 2–4).
Table 2–10. Clock Synthesizer Control Register
BIT
NAME
DESCRIPTION
CC(7)
Control Option
Clock A Select
Logic 0: Input terminals FS(1,0) control clock A
Logic 1: Bits CC(5,4) control clock A
Bit 7 determines control of clock synthesizer A.
CC(6)
Reserved
Bit 6 is reserved. Bit 6 can be read which returns the value written, but does not affect
the function of the device.
CC(5,4)
Register Set Select
(for Clock A)
Logic 00: Reserved
Logic 01: Reserved
Logic 10: Register set C
Logic 11: Register set D
Bits 5 and 4 select which register set configures clock A.
CC(3)
Control Option
Clock B Select
Logic 0: Input terminals FS(1,0) control clock B.
Logic 1: Bits CC(1,0) control clock B.
Bit 3 determines control of clock synthesizer B.
CC(2)
Reserved
Bit 2 is reserved. Bit 2 can be read which returns the value written, but does not affect
the function of the device.
CC(1,0)
Register Set Select
(for Clock B)
Logic 00: Reserved
Logic 01: Reserved
Logic 10: Reserved
Logic 11: Register set D
Bits 1 and 0 select which register set configures clock B.
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