參數(shù)資料
型號(hào)： TVP3409-135
廠商： Texas Instruments, Inc.
英文描述： Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
中文描述： 先進(jìn)的視頻接口盒（雙鎖相環(huán)，視頻接口調(diào)色器真彩色的CMOS）
文件頁數(shù)： 21/57頁
文件大?。?/td> 312K
代理商： TVP3409-135
2–9
2.2.10
Clock Synthesizer Register Sets
The clock synthesizer register sets determine the frequencies of clock synthesizer A (PLLA, OTCLKA) and
clock synthesizer B (PLLB, OTCLKB) for a given reference frequency. There are four sets for OTCLKA and
four sets for OTCLKB. A set of registers is chosen by toggling either the FS(1,0) terminals or the CC(5,4)
or CC(1,0) bits.
Each register set consists of four registers. The four registers have information affecting seven functions
of the clock synthesizer. The feedback divider term (M) together with the reference divider term (N) and
postscaler term (P) determine the frequency according to equation 1 in Section 2.6.4.1, Determining Output
Frequency. The M term is 8 bits, the N term is 6 bits, and the P term is 2 bits.
Table 2–12 and Table 2–14 show the fields associated with each term. The third and fourth registers are
reserved and can be read which returns the values written, but does not affect the function of the device.
The clock synthesizer A register sets are operational on power up. They can be read from or written to by
the MPU at any time and they are not initialized. All of the registers are reset to produce the frequencies in
Table 2–19 upon asserting RESET. To read from or write to these registers, set bit CR0(0) = 1, write
0x40–0x4F to the WMA, and set RS(1,0) = HL. These registers cannot be accessed by state machine
addressing (see Table 2–5 and Table 2–19).
Table 2–11. Clock Synthesizer A Parameters
REGISTER
CONTROL SET
ACCESS
REGISTER
NUMBER
DESCRIPTION
DEFAULT
FREQUENCY
Reserved
A
None
0
25 057 MH
25.057 MHz
Reserved
CC(5,4) = 00 or
FS(1,0) = LL
B
1
Reserved
1
Reserved
None
0
28 189 MH
28.189 MHz
Reserved
CC(5,4) = 01 or
FS(1,0) = LH
C
1
Reserved
1
AC0(7–0)
Read or
Write
0
Feedback divider term (M)
50 114 MH
50.114 MHz
AC1(7,6)
CC(5,4) = 10 or
FS(1,0) = HL
D
1
Postscaler divider term (P)
AC1(5–0)
1
Reference divider term (N)
AD0(7–0)
Read or
Write
0
Feedback divider term (M)
75 170 MH
75.170 MHz
AD1(7,6)
CC(5,4) = 11 or
FS(1,0) = HH
1
Postscaler divider term (P)
AD1(5–0)
1
Reference divider term (N)
Table 2–12. Clock Synthesizer A Register Set Fields
CLOCK REGISTER 0, BITS AND FIELDS
CLOCK REGISTER 1, BITS AND FIELDS
7
6
5
4
M(7–0)
3
2
1
0
7
P(1,0)
6
5
4
3
N(5–0)§
2
1
0
CLOCK REGISTER 2, BITS AND FIELDS
CLOCK REGISTER 3, BITS AND FIELDS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Reserved
Reserved
M(7–0), 8 bits, integer from 0 to 255 (2 is added to this value)
P(1,0), 2 bits, integer from 0 to 3 (these bits indicate the power of 2. See equation 1 in Section 2.5.4.1, Determining
Output Frequency)
§N(5–0), 6 bits, integer from 0 to 63 (2 is added to this value)
相關(guān)PDF資料
PDF描述
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703-135 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703FN VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3409-135CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3409-135FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3409-170CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3409-170FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3703 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC
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