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參數(shù)資料
| 型號： | TVP3026-250 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 11/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-250 |
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1–5
1.4
Ordering Information
TVP3026
– XXX
XXXX
Pixel Clock Frequency Indicator
MUST CONTAIN THREE CHARACTERS:
–135: 135-MHz pixel clock (revision A only)
–175: 175-MHz pixel clock
–220: 220-MHz pixel clock
–250: 250-MHz pixel clock
Device Revision
MUST CONTAIN ONE LETTER:
A
B
Package
MUST CONTAIN THREE LETTERS:
PCE: Plastic, Quad Flat Pack
MDN:Metal, Quad Flat Pack
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
80, 84,
86, 87
AVDD
Analog power. All AVDD terminals must be connected. A separate cutout in the
DVDD plane should be made for AVDD. The DVDD and AVDD planes should be
connected only at a single point through a ferrite bead close to where power enters
the board.
CLK0
106
I
Dot clock 0 TTL input. CLK0 can be selected to drive the dot clock at frequencies
up to 140 MHz. When using the VGA port, the maximum frequency is 85 MHz.
CLK0 can be selected as the latch clock for VGA data and video controls.
(power-up default).
CLK1
107
I
Dot clock 1 TTL input. CLK1 can be selected to drive the dot clock at frequencies
up to 140 MHz.
CLK2, CLK2
108, 109
I
Dual-mode dot clock input. These inputs are emitter-coupled logic
(ECL)-compatible inputs. Alternatively, CLK2 and CLK2 may be used as
individual TTL clock inputs. Programming the clock selection register selects the
chosen configuration. These inputs may be selected as the dot clock up to the
device limit while in the ECL mode or up to 140 MHz in the TTL mode.
COMP1,
COMP2
77, 79
I
Compensation. COMP1 and COMP2 provide compensation for the internal
reference amplifier. A 0.1-
μ
F ceramic capacitor is required between COMP1 and
COMP2. This capacitor must be as close to the device as possible to avoid noise
pick up.
DVDD
2, 18, 39,
40, 45, 65,
117, 137
Digital power. All DVDD terminals must be connected to the digital power plane
with sufficient decoupling capacitors near the TVP3026.
D7–D0
47–54
I/O
MPU interface data bus. Data is transferred in and out of the register map, palette
RAM, and cursor RAM on D7–D0.
NOTE 1: All unused inputs should be tied to a logic level and not allowed to float.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-250AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-250APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-250BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-250BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP3026-250CPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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