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參數(shù)資料
| 型號(hào)： | TVP3010M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface Palette |
| 中文描述： | 視頻接口面板 |
| 文件頁數(shù)： | 15/90頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TVP3010M |
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1–9
1.5
Terminal Functions (TVP3010C and TVP3010M) Continued
TERMINAL
NAME
NO. (FN)
NO. (GA)
REF
53
M12
DESCRIPTION
I/O
Voltage reference for DACs. An internal voltage reference
of nominally 1.235 V is provided, which requires an
external 0.1-
μ
F ceramic capacitor between REF and
analog GND. However, the internal reference voltage can
be overdriven by an externally supplied reference voltage.
A typical connection is shown in Appendix A.
RD
31
B10
I
(TTL
compatible)
Read strobe inputs When cleared to 0, RD initiates a
read from the register map. Reads are performed
asynchronously and are initiated on the low-going edge of
RD (see Figure 3–1).
RS(0–2)
32–34
A12, C10,
B11
I
(TTL
compatible)
Register-select inputs. The RS terminals specify the
location in the register map that is to be accessed (see
Table 2–1).
RS3 [PSEL]
35
C11
I
(TTL
compatible)
Register-select input or port-select input. When configured
as the RS3 input, this terminal has no effect. When
configured as the port-select input, RS3 [PSEL] allows the
creation of VGA or overlay windows in a direct-color
background on a pixel-by-pixel basis.
SCLK
79
K1
O
(TTL
compatible)
Shift clock output. SCLK is selected as a division of the dot
clock input. The output signals are gated off during
blanking, although SCLK is still used internally to
synchronize with the activation of Blank.
SFLAG
62
M8
I
(TTL
compatible)
Split shift register transfer flag. The TVP3010 detects a
low-to-high transition on SFLAG during a blanking
sequence and immediately generates an SCLK pulse. This
early SCLK pulse replaces the first SCLK pulse in the
normal sequence.
SYSBL
60
M9
I
(TTL
compatible)
System blank input. SYSBL is active (low).
HSYNC,
VSYNC
58, 59
M10, L9
I
(TTL
compatible)
Horizontal and vertical sync inputs. These signals
generate the sync level on the green current output. They
are active (low) inputs, but the HSYNCOUT and
VSYNCOUT outputs can be programmed through the
general control register.
VCLK
78
L1
O
(TTL
compatible)
Video clock output. VCLK is the user-programmable
output for synchronization to the graphics processor.
VGABL
61
L8
I
(TTL
capability)
VGA blank input. VGABL is active (low).
VGA(0–7)
65–72
M6, L6, M5,
L5, M4, L4,
M3, M2
I
(TTL
capability)
VGA pass-through bus. These buses can be selected as
the pixel bus for VGA mode, but it does not allow for any
multiplexing.
NOTE 1:
All unused inputs should be tied to a logic level and not be allowed to float.
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