參數(shù)資料
型號(hào): TVP3010-110
廠商: Texas Instruments, Inc.
英文描述: Hardware Cursor, GAMMA Correction VIP(110MHz,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
中文描述: 硬件光標(biāo),伽瑪校正貴賓(110MHz的,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
文件頁(yè)數(shù): 17/100頁(yè)
文件大?。?/td> 571K
代理商: TVP3010-110
2–3
Table 2–2. Indirect Register Map (Extended Registers) (Continued)
INDEX REGISTER
(HEX)
R/W
DEFAULT
(HEX)
REGISTER ADDRESSED
BY INDEX REGISTER
2A
Reserved
2B
Reserved
2C
Reserved
2D
Reserved
2E
Reserved
2F
Reserved
30
R/W
XX
Color-Key OL/VGA Low
31
R/W
XX
Color-Key OL/VGA High
32
R/W
XX
Color-Key Red Low
33
R/W
XX
Color-Key Red High
34
R/W
XX
Color-Key Green Low
35
R/W
XX
Color-Key Green High
36
R/W
XX
Color-Key Blue Low
37
R/W
XX
Color-Key Blue High
38
R/W
10
Color-Key Control Register
39
Reserved-Undefined
3A
R/W
00
Sense Test Register
3B
R
XX
Test Data Register
3C
R
XX
CRC LSB
3D
R
XX
CRC MSB
3E
W
XX
CRC Control Register
3F
R
10
ID Register
FF
W
XX
Reset Register
NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate
from that specified. Reserved-undefined registers are nonexistent locations on
the register map.
2.2
Color Palette
The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM.
This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not
cause any noticeable disturbance on the display.
The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is eight
bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen (8/6 = 0).
If the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.
However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with IMSG176 and
Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs with 0s
after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC
calculation both take data after the output multiplexer, enabling total system verification. The color-palette
access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.
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TVP3010-135 Hardware Cursor, GAMMA Correction VIP(135MHz,高/寬光標(biāo),伽馬校正,視頻接口調(diào)色板)
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