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參數(shù)資料
| 型號(hào)： | TUA6039F-2 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | 3-BAND, VIDEO TUNER, QCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 19/62頁 |
| 文件大?。?/td> | 1024K |
| 代理商： | TUA6039F-2 |
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Data Sheet
26
Revision 2.0, 2007-07-20
TUA 6039F-2, TUA 6037F
Functional Description
3.4.5
I
2C-Bus Interface
Data is exchanged between the processor and the PLL via the I
2C bus. The clock is
generated by the processor (input SCL). Pin SDA functions as an input or output
depending on the direction of the data (open collector, external pull-up resistor). Both
inputs have a hysteresis and a low-pass characteristic, which enhance the noise
immunity of the I
2C bus.
The data from the processor pass through an I
2C bus controller. Depending on their
function the data are subsequently stored in registers. If the bus is free, both lines will be
in the marking state (SDA, SCL are high). Each telegram begins with the start condition
and ends with the stop condition. Start condition: SDA goes low, while SCL remains high.
Stop condition: SDA goes high while SCL remains high. All further information transfer
takes place during SCL = low, and the data is forwarded to the control logic on the
positive clock edge.
The table ’Bit Allocation’ (see Table 8) should be referred to for the following description.
All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which
the control logic returns the SDA line to low (acknowledge condition). The first byte is
comprised of seven address bits. These are used by the processor to select the PLL from
several peripheral components (address select). The LSB bit (R/W) determines whether
data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the first or
third data byte determines whether a divider ratio or control information is to follow. In
each case the second byte of the same data type has to follow the first byte. Appropriate
setting of the test bits will decide whether the band-switch byte or the auxiliary byte will
be transmitted (see Table 11).
If the address byte indicates a READ operation, the PLL generates an acknowledge and
then shifts out the status byte onto the SDA line. If the processor generates an
acknowledge, a further status byte is output; otherwise the data line is released to allow
the processor to generate a stop condition. The status word consists of three bits from
the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS (see
While the supply voltage is applied, a power-on reset circuit prevents the PLL from
setting the SDA line to low, which would block the bus. The power-on reset flag POR is
set at power-on and if V
CC falls below 2 V. It will be reset at the end of a READ operation.
3.4.6
Loop thru
For the tuner prestage alignment a programmable switch is integrated to bypass the
bandpass, the SAW filter driver and the SAW filter. If "Loop thru" is active the mixer
output signal in front of the external bandpass is fed into the IF AGC amplifier as shown
in Figure 5.
相關(guān)PDF資料 |
PDF描述 |
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| TUA6037F | 3-BAND, VIDEO TUNER, QCC48 |
| TUA6039 | 3-BAND, VIDEO TUNER, QCC48 |
| TUA6039-2 | 3-BAND, VIDEO TUNER, QCC48 |
| TUA6037 | 3-BAND, VIDEO TUNER, QCC48 |
| TUA6041-2 | 3-BAND, VIDEO TUNER, QCC48 |
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