參數(shù)資料
型號: TSC80251G2D-L16CED
元件分類: 8位微控制器
英文描述: 8/16-bit Microcontroller with Serial Communication Interfaces
中文描述: 16位產(chǎn)品微控制器的串行通信接口
文件頁數(shù): 20/63頁
文件大?。?/td> 878K
代理商: TSC80251G2D-L16CED
Rev. A - May 7, 1999
20
TSC80251G2D
Table 23. Summary of Logical Instructions (1/2)
Notes:
1. Logical instructions that affect a bit are in Table 29.
2. A shaded cell denotes an instruction in the C51 Architecture.
3. If this instruction addresses an I/O Port (Px, x= 0-3), add 1 to the number of states. Add 2 if it addresses a Peripheral SFR.
4. If this instruction addresses an I/O Port (Px, x= 0-3), add 2 to the number of states. Add 3 if it addresses a Peripheral SFR.
5. If this instruction addresses external memory location, add N+2 to the number of states (N: number of wait states).
6. If this instruction addresses external memory location, add 2(N+2) to the number of states (N: number of wait states).
Logical AND
(1)
Logical OR
(1)
Logical Exclusive OR
(1)
Clear
(1)
Complement
(1)
Rotate Left
ANL <dest>, <src>
ORL <dest>, <src>
XRL <dest>, <src>
CLR A
CPL A
RL A
dest opnd
dest opnd
Λ
src opnd
dest opnd
dest opnd
src opnd
dest opnd
dest opnd
src opnd
(A)
0
(A)
(A)
(A)
n+1
(A)
n
, n= 0..6
(A)
0
(A)
7
(A)
n+1
(A)
n
, n= 0..6
(CY)
(A)
7
(A)
0
(CY)
(A)
n-1
(A)
n
, n= 7..1
(A)
7
(A)
0
(A)
n-1
(A)
n
, n= 7..1
(CY)
(A)
0
(A)
7
(CY)
Binary Mode
Rotate Left Carry
RLC A
Rotate Right
RR A
Rotate Right Carry
RRC A
Mnemonic
<dest>, <src>
(1)
Comments
Source Mode
Bytes
States
Bytes
States
ANL
ORL
XRL
A, Rn
register to ACC
1
1
2
2
A, dir8
Direct address (on-chip RAM or SFR) to ACC
2
1
(3)
2
1
(3)
A, @Ri
Indirect address to ACC
1
2
2
3
A, #data
Immediate data to ACC
2
1
2
1
dir8, A
ACC to direct address
2
2
(4)
3
(4)
2
2
(4)
3
(4)
dir8, #data
Immediate 8-bit data to direct address
3
3
Rmd, Rms
Byte register to byte register
3
2
2
1
WRjd, WRjs
Word register to word register
3
3
2
2
Rm, #data
Immediate 8-bit data to byte register
4
3
3
2
WRj, #data16
Immediate 16-bit data to word register
5
4
4
3
Rm, dir8
Direct address (on-chip RAM or SFR) to byte register
4
3
(3)
3
2
(3)
WRj, dir8
Direct address (on-chip RAM or SFR) to word register
4
4
3
3
Rm, dir16
Direct address (64K) to byte register
5
3
(5)
4
(6)
3
(5)
4
(5)
4
2
(5)
3
(6)
2
(5)
3
(5)
WRj, dir16
Direct address (64K) to word register
5
4
Rm, @WRj
Indirect address (64K) to byte register
4
3
Rm, @DRk
Indirect address (16M) to byte register
4
3
CLR
A
Clear ACC
1
1
1
1
CPL
A
Complement ACC
1
1
1
1
RL
A
Rotate ACC left
1
1
1
1
RLC
A
Rotate ACC left through CY
1
1
1
1
RR
A
Rotate ACC right
1
1
1
1
RRC
A
Rotate ACC right through CY
1
1
1
1
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