參數(shù)資料
型號(hào)： TSC251G2DXXX-L16CED
英文描述： IC CYCLONE III FPGA 80K 780FBGA
中文描述： 微控制器
文件頁(yè)數(shù)： 40/63頁(yè)
文件大?。?/td> 878K
代理商： TSC251G2DXXX-L16CED
40
Rev. A - May 7, 1999
TSC80251G2D
Table 45. Bus Cycles AC Timings; V
DD
= 4.5 to 5.5 V, T
A
= -40 to 85
°
C
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·T
OSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·T
OSC
(N= 1..3).
Symbol
Parameter
12 MHz
16 MHz
24 MHz
Unit
Min
Max
Min
Max
Min
Max
T
OSC
T
LHLL
T
AVLL
T
LLAX
T
RLRH(1)
T
WLWH
T
LLRL(1)
T
LHAX
T
RLDV(1)
T
RHDX(1)
T
RHAX(1)
T
RLAZ(1)
T
RHDZ1
T
RHDZ2
T
RHLH1
T
RHLH2
T
WHLH
T
AVDV1
T
AVDV2
T
AVDV3
T
AXDX
T
AVRL(1)
T
AVWL1
T
AVWL2
T
WHQX
T
QVWH
T
WHAX
1/F
OSC
ALE Pulse Width
83
62
41
ns
78
58
38
ns
(2)
ns
(2)
Address Valid to ALE Low
78
58
37
Address hold after ALE Low
19
11
3
ns
RD#/PSEN# Pulse Width
162
121
78
ns
(3)
ns
(3)
WR# Pulse Width
165
124
81
ALE Low to RD#/PSEN# Low
22
14
6
ns
ALE High to Address Hold
99
70
40
ns
(2)
ns
(3)
RD#/PSEN# Low to Valid Data
146
104
61
Data Hold After RD#/PSEN# High
0
0
0
ns
Address Hold After RD#/PSEN# High
0
0
0
ns
RD#/PSEN# Low to Address Float
0
0
0
ns
Instruction Float After RD#/PSEN# High
45
40
30
ns
Data Float After RD#/PSEN# High
215
165
115
ns
RD#/PSEN# high to ALE High (Instruction)
49
43
31
ns
RD#/PSEN# high to ALE High (Data)
215
169
115
ns
WR# High to ALE High
215
169
115
ns
Address (P0) Valid to Valid Data In
250
175
105
ns
(2)(3)
ns
(2)(3)
ns
(3)
Address (P2) Valid to Valid Data In
306
223
140
Address (P0) Valid to Valid Instruction In
150
109
68
Data Hold after Address Hold
0
0
0
ns
Address Valid to RD# Low
100
70
40
ns
(2)
ns
(2)
ns
(2)
Address (P0) Valid to WR# Low
100
70
40
Address (P2) Valid to WR# Low
158
115
74
Data Hold after WR# High
90
69
32
ns
Data Valid to WR# High
133
102
72
ns
(3)
WR# High to Address Hold
167
125
84
ns
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