參數(shù)資料
型號(hào): TSA1201IFT
廠商: STMICROELECTRONICS
元件分類(lèi): ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 7 X 7 MM, PLASTIC, TQFP-48
文件頁(yè)數(shù): 8/20頁(yè)
文件大小: 349K
代理商: TSA1201IFT
TSA1201
16/20
Figure 9 : DC-coupled 1Vpp analog input
Dynamic characteristics, while not being as
remarkable as for differential configuration, are still
of very good quality. Measurements done at
50Msps, 2MHz input frequency, -1dBFS input
level sum up these performances. A SNR of
63.5dB and an ENOB full Scale of 10.2 bits are
achieved.
IF-sampling
Software radio has become a common mode for
receiving data through RF receivers. Its main
advantage being to digitally implement what was
originally done with analog functions such as
discriminators, demodulation and filtering.
Originally, bipolar process was mainly used
because they provided high transistor transit
frequency, while pure CMOS technology showed
a lower one. With new CMOS process and circuit
topology, higher frequencies are now achieved.
The TSA1201 has been specifically designed to
meet the requirement of sampling at Intermediate
Frequency. For this purpose, the Track-and-Hold
of the first pipeline stage has been built to ensure
the global linearity of the overall ADC to perform
the right characteristics.
Our proprietary Track-and-Hold has a patented
switch control system to enable the performances
not to be degraded as input signal frequency
increases.
As a result, an analog bandwidth of 1GHz is
achieved.
Clock input
The converter quality is very dependant on clock
input accuracy, in terms of aperture jitter; the use
of
low
jitter
crystal
controlled
oscillator
is
recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to always keep the circuit
clocked, to avoid random states, before applying
the supply voltages.
Power consumption optimization
The internal architecture of the TSA1201 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins.
The TSA1201 will combine highest performances
and lowest consumption at 50Msps when Rpol is
equal to 12k
.
At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as well.
The figure 10 sums up the relevant data.
Figure 10 : Analog Current consumption vs. Fs
According value of Rpol polarization resistance
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is recommended for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is essential to prevent noise from
coupling onto the input signal.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
330pF
4.7uF
10nF
Analog
DC
AC+DC
TSA1201
VIN
VINB
INCM
VREFM
VREFP-VREFM = 0.5 V
0.5V power supply
0
20
40
60
80
100
120
140
160
180
200
5
25
456585
Fs(MHz)
R
pol
(k
O
h
m
s
)
0
10
20
30
40
50
60
70
Icca(m
A
)
RPOL
ICCA
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