參數(shù)資料
型號(hào): TSA1201IF
廠商: STMICROELECTRONICS
元件分類: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 7 X 7 MM, PLASTIC, TQFP-48
文件頁數(shù): 4/20頁
文件大?。?/td> 349K
代理商: TSA1201IF
TSA1201 APPLICATION NOTE
12/20
DETAILED INFORMATION
The TSA1201 is a High Speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.
The pipeline structure consists of 11 internal
conversion stages in which the analog signal is
fed and sequentially converted into digital data.
Each 10 first stages consists of an Analog to
Digital converter, a Digital to Analog converter, a
Sample and Hold and a gain of 2 amplifier. A
1.5-bit conversion resolution is achieved in each
stage. The latest stage simply is a comparator.
Each resulting LSB-MSB couple is then time
shifted to recover from the delay caused by
conversion. Digital data correction completes the
processing by recovering from the redundancy of
the (LSB-MSB) couple for each stage. The
corrected data are outputted through the digital
buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the
falling edge of the clock.
The advantages of such a converter reside in the
combination of pipeline architecture and the most
advanced technologies. The highest dynamic
performances are achieved while consumption
remains at the lowest level.
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described in
the following table.
The TSA1201 is pin to pin compatible with the
8bits/40Msps
TSA0801,
the
10bits/25Msps
TSA1001 and the 10bits/50Msps TSA1002. This
ensures a conformity within the product family and
above all, an easy upgrade of the application
OPERATIONAL MODES DESCRIPTION
Data Format Select (DFSB)
When set to low level (VIL), the digital input DFSB
provides a two’s complement digital output MSB.
This can be of interest when performing some
further signal processing.
When set to high level (VIH), DFSB provides a
standard binary output coding.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a
low level again, the data are then present on the
output with a very short Ton delay.
Therefore, this allows the chip select of the device.
The timing diagram summarizes this functionality.
Inputs
Outputs
Analog input differential level
DFSB
OEB
SRC
OR
DR
Most Significant Bit (MSB)
(VIN-VINB)
>
RANGE
H
L
X
H
CLK
D11
-RANGE
>
(VIN-VINB)
H
L
X
H
CLK
D11
RANGE> (VIN-VINB) >-RANGE
H
L
X
L
CLK
D11
(VIN-VINB)
>
RANGE
L
X
H
CLK
D11 Complemented
-RANGE
>
(VIN-VINB)
L
X
H
CLK
D11 Complemented
RANGE> (VIN-VINB) >-RANGE
L
X
L
CLK
D11 Complemented
X
H
X
HZ
X
H
X
CLK
25Msps compliant slew rate
X
L
X
CLK
50Msps compliant slew rate
相關(guān)PDF資料
PDF描述
TSA1201IFT 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
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TSA1203IF 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QFP48
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參數(shù)描述
TSA1201IFT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:12-BIT, 50MSPS, 150mW A/D CONVERTER
TSA1203 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL-CHANNEL, 12-BIT, 40MSPS, 230mW A/D CONVERTER
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TSA1203IF 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Channel 12-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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