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| 型號(hào)： | TSA1005I-40IF |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, TQFP-48 |
| 文件頁(yè)數(shù)： | 8/22頁(yè) |
| 文件大?。?/td> | 540K |
| 代理商： | TSA1005I-40IF |
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TSA1005
16/22
NO
T
FOR
NEW
DESI
G
N
Clock input
The TSA1005 performance is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to always keep the circuit
clocked, even at the lowest specified sampling
frequency of 0.5Msps, before applying the supply
voltages.
Power consumption
So as to optimize both performance and power
consumption of the TSA1005 according the
sampling frequency, a resistor is placed between
IPOL and the analog Ground pins. Therefore, the
total dissipation is adjustable from 5Msps up to
40Msps.
The TSA1005 will combine highest performances
and lowest consumption at 20Msps when Rpol is
equal to 70k
, at 40Msps when Rpol is equal to
35k
. These values are nevertheless dependant
on application and environment.
At lower sampling frequency range, this value of
resistor may be adjusted in order to decrease the
analog
current
without
any
degradation
of
dynamic performances.
The figure 6 sums up the relevant data.
Figure 6: analog current consumption
optimization depending on Rpol value
APPLICATION
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is recommended for high speed circuit
applications to provide low inductance and low
resistance common return.
The separation of the analog signal from the
digital part is mandatory to prevent noise from
coupling
onto
the
input
signal.
The
best
compromise is to connect from one part AGND,
DGND, GNDBI in a common point whereas
GNDBE must be isolated. Similarly, the power
supplies AVCC, DVCC and VCCBI must be
separated from the VCCBE one.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
Digital Interface application
Thanks to its wide external buffer power supply
range, the TSA1005 is perfectly suitable to plug in
to 2.5V low voltage DSPs or digital interfaces as
well as to 3.3V ones.
Medical Imaging application
Driven by the demand of the applications requiring
nowadays either portability or high degree of par-
allelism (or both), this product has been devel-
oped to satisfy medical imaging, and telecom in-
frastructures needs.
As a typical system diagram shows figure 10, a
narrow input beam of acoustic energy is sent into
a living body via the transducer and the energy re-
flected back is analyzed.
0
10
20
30
40
50
60
70
80
90
100
5
1525
3545
55
Fs (MHz)
Icca
(
m
A
)
0
50
100
150
200
250
Rpol
(
k
O
h
m
s
)
RPOL
ICCA
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