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參數資料
| 型號： | TSA1001CF |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數： | 8/20頁 |
| 文件大?。?/td> | 218K |
| 代理商： | TSA1001CF |
TSA1001
16/20
NO
T
FOR
NEW
DESI
G
N
Figure 9 : DC-coupled 1Vpp analog input
Dynamic characteristics, while not being as
remarkable as for differential configuration, are
still of very good quality.
Clock input
The converter quality is very dependant on clock
input accuracy, in terms of aperture jitter; the use
of
low
jitter
crystal
controlled
oscillator
is
recommended.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to keep the circuit clocked, to
avoid random states, before applying the supply
voltages.
Power consumption optimization
The internal architecture of the TSA1001 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins.
The TSA1001 will combine highest performances
and lowest consumption at 25Msps when Rpol is
equal to 25k
.
At lower sampling frequency range (< 10Msps),
this value of resistor may be adjusted in order to
decrease
the
analog
current
without
any
degradation of dynamic performances.
As an example, 10mW total power consumption is
achieved at 5 Msps with Rpol equal to 390k
.
The table below sums up the relevant data.
Total power consumption optimization
depending on Rpol value
Linearity, distortion performance towards
Clock Duty Cycle variation
The TSA1001 has an outstanding behaviour
towards clock duty cycle variation.
Linearity vs. Duty cycle
Fs=25MSPS; Icca=11mA; Fin=10MHz
Distortion vs. Duty cycle
Fs=25MSPS; Icca=11mA; Fin=10MHz
Fs (Msps)
5
15
25
Rpol (
k
)
390
40
25
Optimized
power (mW)
10
25
35
330pF
4.7uF
10nF
Analog
DC
AC+DC
TSA1001
VIN
VINB
INCM
VREFM
VREFP-VREFM = 0.5 V
0.5V power supply
50
52
54
56
58
60
62
64
66
68
70
30
40
50
60
70
Duty Cycle (%)
Dynam
ic
par
a
m
e
te
rs
(
d
B)
8
8.2
8.4
8.6
8.8
9
9.2
9.4
9.6
9.8
10
E
N
O
B
(b
its
)
SINAD
ENOB
SNR
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
30
40
50
60
70
Duty Cycle (%)
D
y
n
a
mi
c
P
a
ra
me
te
rs
(
d
B
)
SFDR
THD
相關PDF資料 |
PDF描述 |
|---|---|
| TSA1002CFT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1002CF | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1002IF | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1002IFT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005-20IFT | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TSA1001CFT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 25MSPS, 35mW A/D CONVERTER |
| TSA1001IF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 25MSPS, 35mW A/D CONVERTER |
| TSA1001IFT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 25MSPS, 35mW A/D CONVERTER |
| TSA1002 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 50MSPS, 50mW A/D CONVERTER |
| TSA1002_04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 50MSPS, 50mW A/D CONVERTER |
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