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參數(shù)資料
| 型號： | TS87C51RD2-VCL |
| 廠商： | International Rectifier |
| 英文描述： | High Performance 8-bit Microcontroller |
| 中文描述： | 高性能8位微控制器 |
| 文件頁數(shù)： | 50/85頁 |
| 文件大?。?/td> | 762K |
| 代理商： | TS87C51RD2-VCL |
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50
4188E–8051–08/06
AT/TS8xC51Rx2
7.1
Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with exter-
nal program or data memory. Nevertheless, during internal code execution, ALE signal is still
generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer
output but remains active during MOVX and MOVC instructions and external fetches. During
ALE disabling, ALE pin is weakly pulled high.
Table 7-2.
AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = XXXX XX00b
Not bit addressable
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EXTRAM
AO
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
EXTRAM
EXTRAM bit
See Table 6-1.
0
AO
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
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|---|---|
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