參數(shù)資料
型號(hào)： TS87C51RB2-EED
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, MICROCONTROLLER, PQFP44
封裝： 1.40 MM HEIGHT, VQFP-44
文件頁(yè)數(shù)： 42/74頁(yè)
文件大?。?/td> 689K
代理商： TS87C51RB2-EED
Rev. C - 06 March, 2001
47
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
Table 24. WDTPRG Register
WDTPRG Address (0A7h)
Reset value XXXX X000
6.10.2. WDT during Power Down and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51Rx2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51Rx2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit Number
Bit
Mnemonic
Description
7
T4
Reserved
Do not try to set or clear this bit.
6
T3
5
T2
4
T1
3
T0
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2
S1
S0
Selected Time-out
00
0
(214 - 1) machine cycles, 16.3 ms @ 12 MHz
00
1
(215 - 1) machine cycles, 32.7 ms @ 12 MHz
01
0
(216 - 1) machine cycles, 65.5 ms @ 12 MHz
01
1
(217 - 1) machine cycles, 131 ms @ 12 MHz
10
0
(218 - 1) machine cycles, 262 ms @ 12 MHz
10
1
(219 - 1) machine cycles, 542 ms @ 12 MHz
11
0
(220 - 1) machine cycles, 1.05 s @ 12 MHz
11
1
(221 - 1) machine cycles, 2.09 s @ 12 MHz
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