參數(shù)資料
型號： TS86101G2BVGL
廠商： E2V TECHNOLOGIES PLC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255
封裝： HERMETIC SEALED, CERAMIC, BGA-255
文件頁數(shù)： 15/57頁
文件大?。?/td> 1030K
代理商： TS86101G2BVGL
22
0992D–BDC–04/09
TS86101G2B
e2v semiconductors SAS 2009
Figure 5-3.
Data to Data Clock Forbidden Area
5.3
Phase Relationship Between Data Ready and CW_IN Clock Input
There is a forbidden time range in the phase relation between Data Ready and the CW_IN master clock.
This forbidden zone occurs when active rising edges of CW_IN and Data Ready do not comply with the
setup and hold times (see Figure 5-4 on page 22). Within this forbidden zone, the data is stored in the
second bank of master latches at the time when the first outputs of slave latches switch (acquisition of
next incoming data). Within this critical time range of 600 ps, data pattern throughput transmission errors
may occur.
To satisfy setup and hold times, the phase of the Data Ready input (D_CK_T to D_CK_F) can be
adjusted by choosing one of the 16 DSP clock shift positions (assuming that the DSP providing the data
and Data Ready signals to the MUXDAC is clocked by the MUXDAC DSP clock’s output signal).
Figure 5-4.
Data Ready (D_CK) to CW_IN Master Clock Timing
If the D_CK clock edge occurs within the forbidden zone, there is an ambiguity on the data to be trans-
ferred from the first to the second bank of latch (data N or data N + 1).
Tsetup
Thold
Tsetup
Thold
Tsetup
Tthold
allowed
1.2 ns max
forbidden
Data
Clock
forbidden
Thold
Tsetup
CW_IN
D_CK
Forbidden area for rising edge
of D_CK = 600 ps max
2.5 ns
3.1 ns
1
2
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