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參數(shù)資料
| 型號(hào)： | TS86101G2BCGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, CBGA255 |
| 封裝： | HERMETIC SEALED, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 13/57頁 |
| 文件大?。?/td> | 1030K |
| 代理商： | TS86101G2BCGL |
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20
0992D–BDC–04/09
TS86101G2B
e2v semiconductors SAS 2009
5.
Functional Description
5.1
Device Overview
The TS86101G2B is a 10-bit 1.2 Gsps DAC with an integrated 4:1 input MUX, designed for synthesiza-
tion of broadband signals, with enhanced linearity and band flatness performances.
The TS86101G2B is manufactured using full Si bipolar technology. Due to its integrated input 4:1 MUX,
this digital-to-analog converter enables the user to address data rates of only of the effective sampling
frequency (up to 350 Msps input rate), facilitating its interface with state-of-the art FPGAs, ASICs and
DSPs.
The device requires an input Data Ready clock for the data acquisition as well as an output DSP clock,
used for synchronization with the DSP/FPGA/ASIC. This DSP clock is phase programmable thanks to
the <CS_0;CS_3> 4-bit clock phase shift select function of the device.
The analog output is 2 Vpp in differential mode or 1 Vpp in single-ended mode and a diode pin is pro-
vided for die junction temperature monitoring.
Table 5-1.
Description of Functions
Name
Function
V
EEA
Analog power supply
V
EED
Digital power supply
V
CCD
Digital power supply
AGND
Analog ground
DGND
Digital ground
<A0_T:A9_T>
<A0_F:A9_F>
Differential input data port A
<B0_T:B9_T>
<B0_F:B9_F>
Differential input data port B
<C0_T:C9_T>
<C0_F:C9_F>
Differential input data port C
<D0_T:D9_T>
<D0_F:D9_F>
Differential input data port D
OUT_T,OUT_F
Differential analog output
D_CK_T, D_CK_F
Differential Data Ready clock inputs
DSP_CK_T
DSP_CK_F
Differential DSP clock output
CW_IN_T
CW_IN_F
Differential independent master clock input
<CS_0:CS_3>
Shift select for DSP clock (TTL)
DIODE
Die junction temperature monitoring
GA
Gain adjust (to be connected to the REF pin)
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