參數資料
型號: TS86101G2BCGL
廠商: ATMEL CORP
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 10-BIT DAC, PBGA255
封裝: CBGA-255
文件頁數: 12/57頁
文件大?。?/td> 1119K
代理商: TS86101G2BCGL
2
5343C–BDC–03/06
TS86101G2B
1.
Description
The TS86101G2B is a 10-bit 1.2 Gsps DAC with an integrated 4:1 multiplexer, allowing easy interfacing with standard
FPGAs. The enhanced linearity and Noise Power Ratio (NPR) performance (9.5 bits equivalent at 1.2 Gsps) over 550 MHz
instantaneous bandwidth make this product particularly suitable for high-end applications such as arbitrary waveform gen-
erators and broadband DDS systems.
2.
Specifications
Notes:
1. Maximum ratings are limiting values only (referenced to GND = 0V), and are to be applied individually, while other parame-
ters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a
thermal heat sink is mandatory (refer to ”Thermal and Moisture Characteristics” on page 36.)
2. Maximum ratings enable active inputs with MUXDAC power off.
3. Maximum ratings enable floating inputs with MUXDAC power on.
Table 2-1.
Absolute Maximum Ratings
Parameter
Symbol
Comments
Value
Unit
Positive digital power supply
V
CCD
GND to 6.0
V
Negative digital power supply
VEED
-6.0 to GND
V
Negative analog power supply
VEEA
-6.0 to GND
V
Maximum difference between
negative supply voltages
VEED - VEEA
0.7
V
Digital inputs
Port Y = A/B/C/D
<Y0_T; Y9_T> or
<Y0_F; Y9_F>
VIL > -0.25
VIH < 5.5
V
Maximum difference digital inputs
Port Y = A/B/C/D
<Y0_T; Y9_T>
<Y0_F; Y9_F>
V
IH - VIL < 1.4
Vp
Data ready clock input
D_CK_T, D_CK_F
VIL > -0.25
VIH < 5.5
V
Maximum difference between
D_CK_T and D_CK_F
D_CK_T, D_CK_F
VIH - VIL < 1.4
Vp
Master clock input
CW_IN_T, CW_IN_F
VIL > -3.5
V
IH < 0.75
V
Maximum difference between
CW_IN_T and CW_IN_F
CW_IN_T, CW_IN_F
V
IH - VIL < 1.2
Vp
Digital shift select voltage
CS
GND to V
CCD
V
Maximum junction temperature
TJ
135
°C
Storage temperature
Tstg
-65 to 150
°C
Lead temperature
T
balls
250
(during 10s max.)
°C
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