參數(shù)資料
型號: TS83148VZ
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28
封裝: CERAMIC, DFP-28
文件頁數(shù): 13/16頁
文件大?。?/td> 551K
代理商: TS83148VZ
TS83148
6/16
11. FUNCTIONAL DESCRIPTION
H The TS83148 uses an innovative architecture featuring folding and serial interpolation.
H A fully differential front end T/H allows good performances over a wide range of input frequencies.
H Analog input : Versatile operation mode :
- Single ended input : range 2.5 V
± 0.5 V on VIN, 2.5 V on VREF.
- Differential input : range 2.5
± 0.25 V on VIN and VREF, recommended use for differential input mode.
VREF
VIN
2.5 V (VOUT)
Input signal
± 0.5 V
1:1
12. SWITCHING PERFORMANCES - See Figure 1
Parameter
Test level
Symbol
Min
Typ
Max
Unit
Clock pulse width (high)
TC1
TBD
8
500
nS
Clock pulse width (low)
TC2
TBD
8
500
nS
Aperture delay
(Note 1)
TA
–1.3
nS
Aperture uncertainty
(Note 1)
Jitter
20
pS (rms)
Output delay
(Notes 1 and 2)
TOD
6
nS
Nap recovery time
NTR
200
nS
Note 1 : See definition of terms
Note 2
Outputs connected to a single LS latch - Cload < 10 pF
TC1
DATA N
DIGITAL
OUTPUTS
TC2
DATA N–1
DATA N+1
DATA N+2
CLK
TA
X
N+1
X
N+2
X
N+3
PIPELINE DELAY (TPD) : 0.5 CLOCK PERIOD
N
VIN
TOD
Figure 1 : TS83148 TIMING DIAGRAM
相關(guān)PDF資料
PDF描述
TS83148MZ 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28
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TS83148VZT 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDFP28
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